ZHCSJK5C January 2018 – October 2020 TCAN4550-Q1
The TCAN4550-Q1 uses 32 bit accesses. The TCAN4550-Q1 provides 2K bytes of MRAM that is fully configurable for TX/RX buffer/FIFO as needed based upon the system needs. To avoid ECC errors right after initialization, the MRAM should be zeroed out during the initialization, power up, power on reset and wake events, a process thus ensuring ECC is properly calculated.
At power up, MRAM values are unknown and thus ECC values is not valid. It is important that at least 2 words (8 bytes) of payload data be written into any TX buffer element, even if the DLC is less than 8. Failure to do this results in a M_CAN BEU error, which puts the TCAN4550-Q1 device into initialization mode, and require user intervention before CAN communication can continue. One way to avoid this, the MRAM should be zeroed out after power up, a power on reset or coming out of sleep mode.