ZHCSJK5C January 2018 – October 2020 TCAN4550-Q1
During a UVIO, UVCCOUT or TSD fault the TCAN4550-Q1 automatically does the following to keep the M_CAN core in a known state. A write of 1 to CCCR.INIT will be issued anytime there is a transition from Normal → Standby. Any currently pending TX or RX processing is halted. Once the device re-enters Normal mode, a write of 0 to CCCR.INIT is issued, and any pending messages (TXBRP active bits) is automatically transmitted.