ZHCSJK5C January 2018 – October 2020 TCAN4550-Q1
The TCAN4550-Q1 has three methods the failsafe feature is used in order to reduce node power consumption for a node system issue. Failsafe is the method the device uses to enter sleep mode from various other modes when specific issues arise. This feature uses the Sleep Wake Error (SWE) timer to determine if the node processor can communicate to the TCAN4550-Q1. The SWE timer is default enabled through the SWE_DIS; 16'h0800 = 0 but can be disabled by writing a one to this bit. Even when the timer is disabled, a power on reset re-enables the timer and thus be active. Failsafe Feature is default disabled but can be enabled by writing a one to 16'h0800, FAILSAFE_EN.
Upon power up the SWE timer starts, tINACTIVE, the processor has typically four minutes to configure the TCAN4550-Q1, clear the PWRON flag or configure the device for normal mode; see Figure 8-14. This feature cannot be disabled. If the device has not had the PWRON flag cleared or been placed into normal mode, it enters sleep mode. The device wakes up if the CAN bus provides a WUP or a local wake event takes place, thus entering standby mode. Once in standby mode tSILENCE and tINACTIVE timers starts. If tINACTIVE expires, the device re-enters sleep mode.
The second failure mechanism that causes the device to use the failsafe feature, if enabled, is when the device receives a CANINT, CAN bus wake (WUP) or WAKE pin (LWU), while in sleep mode such that the device leaves sleep mode and enters standby mode. The processor has four minutes to clear the flags and place the device into normal mode. If this does not happen the device enters sleep mode.
The third failure mechanism that causes the device to use the failsafe feature is when in standby or normal mode and the CANSLNT flag persists for tINACTIVE, the device enters sleep mode. Examples of events that could create this are CLKIN or Crystal stops working, processor is no longer working and not able to exercise the SPI bus, a go-to-sleep command comes in and the processor is not able to receive it or is not able to respond. See state diagram Figure 8-15.