ZHCSJK5D January   2018  – June 2022 TCAN4550-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specification
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC ESD and ISO Transient Specification
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VIO Pin
      3. 8.3.3  VCCOUT Pin
      4. 8.3.4  GND
      5. 8.3.5  INH Pin
      6. 8.3.6  WAKE Pin
      7. 8.3.7  FLTR Pin
      8. 8.3.8  RST Pin
      9. 8.3.9  OSC1 and OSC2 Pins
      10. 8.3.10 nWKRQ Pin
      11. 8.3.11 nINT Interrupt Pin
      12. 8.3.12 GPIO1 Pin
      13. 8.3.13 GPO2 Pin
      14. 8.3.14 CANH and CANL Bus Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Sleep Mode
        1. 8.4.3.1 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
        2. 8.4.3.2 Local Wake-Up (LWU) via WAKE Input Terminal
      4. 8.4.4 Test Mode
      5. 8.4.5 Failsafe Feature
      6. 8.4.6 Protection Features
        1. 8.4.6.1 Watchdog Function
        2. 8.4.6.2 Driver and Receiver Function
        3. 8.4.6.3 Floating Terminals
        4. 8.4.6.4 TXD_INT Dominant Timeout (DTO)
        5. 8.4.6.5 CAN Bus Short Circuit Current Limiting
        6. 8.4.6.6 Thermal Shutdown
        7. 8.4.6.7 Under-Voltage Lockout (UVLO) and Unpowered Device
          1. 8.4.6.7.1 UVSUP and UVCCOUT
          2. 8.4.6.7.2 UVIO
          3. 8.4.6.7.3 Fault and M_CAN Core Behavior:
      7. 8.4.7 CAN FD
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Chip Select Not (nCS):
        2. 8.5.1.2 SPI Clock Input (SCLK):
        3. 8.5.1.3 SPI Data Input (SDI):
        4. 8.5.1.4 SPI Data Output (SDO):
      2. 8.5.2 Register Descriptions
    6. 8.6 Register Maps
      1. 8.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F
        1. 8.6.1.1 DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]
        2. 8.6.1.2 DEVICE_ID2[31:0] (address = h0004) [reset = h30353534]
        3. 8.6.1.3 Revision (address = h0008) [reset = h00110201]
        4. 8.6.1.4 Status (address = h000C) [reset = h0000000U]
        5. 8.6.1.5 SPI Error status mask (address = h0010) [reset = h00000000]
      2. 8.6.2 Device Configuration Registers: 16'h0800 to 16'h08FF
        1. 8.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]
        2. 8.6.2.2 Timestamp Prescaler (address = h0804) [reset = h00000002]
        3. 8.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]
        4. 8.6.2.4 Test Register (address = h080C) [reset = h00000000]
      3. 8.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
        1. 8.6.3.1 Interrupts (address = h0820) [reset = h00100000]
        2. 8.6.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]
        3. 8.6.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
      4. 8.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF
        1. 8.6.4.1  Core Release Register (address = h1000) [reset = hrrrddddd]
        2. 8.6.4.2  Endian Register (address = h1004) [reset = h87654321]
        3. 8.6.4.3  Customer Register (address = h1008) [reset = h00000000]
        4. 8.6.4.4  Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
        5. 8.6.4.5  Test Register (address = h1010 ) [reset = h00000000]
        6. 8.6.4.6  RAM Watchdog (address = h1014) [reset = h00000000]
        7. 8.6.4.7  Control Register (address = h1018) [reset = 0000 0019]
        8. 8.6.4.8  Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
        9. 8.6.4.9  Timestamp Counter Configuration (address = h1020) [reset = h00000000]
        10. 8.6.4.10 Timestamp Counter Value (address = h1024) [reset = h00000000]
        11. 8.6.4.11 Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]
        12. 8.6.4.12 Timeout Counter Value (address = h102C) [reset = h0000FFFF]
        13. 8.6.4.13 Reserved (address = h1030 - h103C) [reset = h00000000]
        14. 8.6.4.14 Error Counter Register (address = h1040) [reset = h00000000]
        15. 8.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]
        16. 8.6.4.16 Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]
        17. 8.6.4.17 Reserved (address = h104C) [reset = h00000000]
        18. 8.6.4.18 Interrupt Register (address = h1050) [reset = h00000000]
        19. 8.6.4.19 Interrupt Enable (address = h1054) [reset = h00000000]
        20. 8.6.4.20 Interrupt Line Select (address = h1058) [reset = h00000000]
        21. 8.6.4.21 Interrupt Line Enable (address = h105C) [reset = h00000000]
        22. 8.6.4.22 Reserved (address = h1060 - h107C) [reset = h00000000]
        23. 8.6.4.23 Global Filter Configuration (address = h1080) [reset = h00000000]
        24. 8.6.4.24 Standard ID Filter Configuration (address = h1084) [reset = h00000000]
        25. 8.6.4.25 Extended ID Filter Configuration (address = h1088) [reset = h00000000]
        26. 8.6.4.26 Reserved (address = h108C) [reset = h00000000]
        27. 8.6.4.27 Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]
        28. 8.6.4.28 High Priority Message Status (address = h1094) [reset = h00000000]
        29. 8.6.4.29 New Data 1 (address = h1098) [reset = h00000000]
        30. 8.6.4.30 New Data 2 (address = h109C) [reset = h00000000]
        31. 8.6.4.31 Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]
        32. 8.6.4.32 Rx FIFO 0 Status (address = h10A4) [reset = h00000000]
        33. 8.6.4.33 Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]
        34. 8.6.4.34 Rx Buffer Configuration (address = h10AC) [reset = h00000000]
        35. 8.6.4.35 Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]
        36. 8.6.4.36 Rx FIFO 1 Status (address = h10B4) [reset = h00000000]
        37. 8.6.4.37 Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]
        38. 8.6.4.38 Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]
        39. 8.6.4.39 Tx Buffer Configuration (address = h10C0) [reset = h00000000]
        40. 8.6.4.40 Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]
        41. 8.6.4.41 Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]
        42. 8.6.4.42 Tx Buffer Request Pending (address = h10CC) [reset = h00000000]
        43. 8.6.4.43 Tx Buffer Add Request (address = h10D0) [reset = h00000000]
          1. 8.6.4.43.1  Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]
          2. 8.6.4.43.2  Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
          3. 8.6.4.43.3  Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]
          4. 8.6.4.43.4  Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]
          5. 8.6.4.43.5  Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
          6. 8.6.4.43.6  Reserved (address = h10E8) [reset = h00000000]
          7. 8.6.4.43.7  Reserved (address = h10EC) [reset = h00000000]
          8. 8.6.4.43.8  Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]
          9. 8.6.4.43.9  Tx Event FIFO Status (address = h10F4) [reset = h00000000]
          10. 8.6.4.43.10 Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]
          11. 8.6.4.43.11 Reserved (address = h10FC) [reset = h00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Design Consideration
      1. 9.1.1 Crystal and Clock Input Requirements
      2. 9.1.2 Bus Loading, Length and Number of Nodes
      3. 9.1.3 CAN Termination
        1.       Termination
        2. 9.1.3.1 CAN Bus Biasing
      4. 9.1.4 INH Brownout Behavior
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Requirements
      2. 9.2.2 Detailed Design Procedures
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 CAN Transceiver Physical Layer Standards:
        2. 12.1.1.2 EMC requirements:
        3. 12.1.1.3 Conformance Test requirements:
        4. 12.1.1.4 Support Documents
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF

The following tables provide the CAN FD programming register sets starting at 16'h1000.

The MRAM and start address for the following registers has special consideration:

  • SIDFC (0x1084)
  • XIDFC (0x1088)
  • RXF0C (0x10A0)
  • RXF1C (0x10B0)
  • TXBC (0x10C0)
  • TXEFC (0x10F0)

The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a write to ensure this behavior.

When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired start address is 0x8634, then bits SA[15:0] will be 0x0634.

Table 8-23 Legend
CodeDescription
RRead
CClear on Write
ddate
nValue after Reset
pProtected Set
PProtected Write
rRelease
SSet on Read
tTest Value
UUndefined
WWrite
XReset on Read
Table 8-24 CAN FD Register Set
ADDRESSSYMBOLNAMERESETACC
1000CRELCore Release Registerrrrd ddddR
1004ENDNEndian Register8765 4321R
1008CUSTCustomer Register0000 0000R
100CDBTPData Bit Timing & Prescaler Register0000 0A33RP
1010TESTTest Register0000 0000RP
1014RWDRAM Watchdog0000 0000RP
1018CCCRCC Control Register0000 0019RWPp
101CNBTPNominal Bit Timing & Prescaler Register0600 0A03RP
1020TSCCTimestamp Counter Configuration0000 0000RP
1024TSCVTimestamp Counter Value0000 0000RC
1028TOCCTimeout Counter ConfigurationFFFF 0000RP
102CTOCVTimeout Counter Value0000 FFFFRC
1030RSVDReserved0000 0000R
1034RSVDReserved0000 0000R
1038RSVDReserved0000 0000R
103CRSVDReserved0000 0000R
1040ECRError Counter Register0000 0000RX
1044PSRProtocol Status Register0000 0707RXS
1048TDCRTransmitter Delay Compensation Register0000 0000RP
104CRSVDReserved0000 0000R
1050IRInterrupt Register0000 0000RW
1054IEInterrupt Enable0000 0000RW
1058ILSInterrupt Line Select0000 0000RW
105CILEInterrupt Line Enable0000 0000RW
1060RSVDReserved0000 0000R
1064RSVDReserved0000 0000R
1068RSVDReserved0000 0000R
106CRSVDReserved0000 0000R
1070RSVDReserved0000 0000R
1074RSVDReserved0000 0000R
1078RSVDReserved0000 0000R
107CRSVDReserved0000 0000R
1080GFCGlobal Filter Configuration0000 0000RP
1084SIDFCStandard ID Filter Configuration0000 0000RP
1088XIDFCExtended ID Filter Configuration0000 0000RP
108CRSVDReserved0000 0000R
1090XIDAMExtended ID and MASK1FFF FFFFRP
1094HPMSHigh Priority Message Status0000 0000R
1098NDAT1New Data 10000 0000RW
109CNDAT2New Data 20000 0000RW
10A0RXF0CRx FIFO 0 Configuration0000 0000RP
10A4RXF0SRx FIFO 0 Status0000 0000R
10A8RXF0ARx FIFO 0 Acknowledge0000 0000RW
10ACRXBCRx Buffer Configuration0000 0000RP
10B0RXF1CRx FIFO 1 Configuration0000 0000RP
10B4RXF1SRx FIFO 1 Status0000 0000R
10B8RXF1ARx FIFO 1 Acknowledge0000 0000RW
10BCRXESCRx Buffer/FIFO Element Size Configuration0000 0000RP
10C0TXBCTx Buffer Configuration0000 0000RP
10C4TXFQSTx FIFO/Queue Status0000 0000R
10C8TXESCTx Buffer Element Size Configuration0000 0000RP
10CCTXBRPTx Buffer Request Pending0000 0000R
10D0TXBARTx Buffer Add Request0000 0000RW
10D4TXBCRTx Buffer Cancellation Request0000 0000RW
10D8TXBTOTx Buffer Transmission Occurred0000 0000R
10DCTXBCFTx Buffer Cancellation Finished0000 0000R
10E0TXBTIETx Buffer Transmission Interrupt Enable0000 0000RW
10E4TXBCIETx Buffer Cancellation Finished Interrupt Enable0000 0000RW
10E8RSVDReserved0000 0000R
10ECRSVDReserved0000 0000R
10F0TXEFCTx Event FIFO Configuration0000 0000RP
10F4TXEFSTx Event FIFO Status0000 0000R
10F8TXEFATx Event FIFO Acknowledge0000 0000RW
10FCRSVDReserved0000 0000R
Table 8-25 CAN FD Register Set Description
OffsetNameBit Pos.MSBLSBAccess
1000CREL7:0Day[7:0] (two digit, BCD-Coded)R
15:8Month[15:8] (two digit, BCD-Coded)R
23:16SUBSTEP[7:4] (One digit, BCD-Coded)Year[3:0] (one digit, BCD-Coded)R
31:24REL[7:4] (One digit, BCD-Coded)STEP[3:0] (one digit, BCD-Coded)R
1004ENDN7:0ETV[7:0] (Endianness Test Value)R
15:8ETV[15:8] (Endianness Test Value)R
23:16ETV[23:16] (Endianness Test Value)R
31:24ETV[31:24] (Endianness Test Value)R
1008CUST7:0
15:8
23:16
31:24
100CDBTP7:0DTSEG2(Data Time Seg before Sample Point)DSJW (Data (Re)Synchronization Jump Width)RP
15:8ReservedDTSEG1(Data Time Seg before Sample Point)RP
23:16TDCReservedDBRP (Data Bit Rate Prescaler)RP
31:24ReservedR
1010TEST7:0RXTXLBCKReservedRP-U
15:8ReservedR
23:16ReservedR
31:24ReservedR
1014RWD7:0WDC (Watchdog Configuration)RP
15:8WDV (Watchdog Counter Value)R
23:16ReservedR
31:24ReservedR
1018CCCR7:0TESTDARMONCSRCSAASMCCEINITRWp
15:8NISOTXPEFBIPXHDReservedBRSEFDOERP
23:16ReservedR
31:24ReservedR
101CNBTP7:0ReservedNTSEG2 (Nominal time Segment After Sample Point)RP
15:8NTSEG1 (Nominal Time Segment Before Sample Point)RP
23:16NBRP[7:0] (Nominal Bit Rate Prescaler)RP
31:24NSJW[6;0] (Nominal (RE)Synchronization Jump Width)NBRP[8]RP
1020TSCC7:0ReservedTSS[1:0] Timestamp SelectRP
15:8ReservedR
23:16ReservedTCP (Timestamp Counter Prescaler)RP
31:24ReservedR
1024TSCV7:0TSC[15:0] (Timestamp Counter)RC
15:8RC
23:16ReservedR
31:24ReservedR
1028TOCC7:0ReservedTOS (Timeout SEL)ETOCRP
15:8ReservedR
23:16TOP[15:0] (Timeout Period)RP
31:24RP
102CTOCV7:0TOC[15:0] (Timeout Counter)RC
15:8RC
23:16ReservedR
31:24ReservedR
1030 – 103CRSVD31:0ReservedR
1040 ECR 7:0 TEC (Transmit Error Counter) R
15:8REC (Receive Error Counter)R
23:16CEL (CAN Error Logging)X
31:24ReservedR
1044PSR7:0BOEWEPACT (Activity)LEC (Last Error Code)RS
15:8ReservedPXERFDFRBRSRESIDLEC (Data Phase Last Error Code)RSX
23:16ReservedTDCV[6:0] (Transmitter Delay Compensation Value)R
31:24ReservedR
1048TDCR7:0ReservedTDCF (Transmitter Delay Compensation Filter Window Length)RP
15:8ReservedTDCO (Transmitter Delay Compensation Offset)RP
23:16ReservedR
31:24ReservedR
104CRSVD31:0ReservedR
1050IR7:0RF1LRF1FRF1WRF1NRF0LRF0FRF0WRF0NR/W
15:8TEFLTEFFTEFWTEFNTFETCFTCHPMR/W
23:16EPELOBEUBECDRXTOOMRAFTSWR/W
31:24ReservedARAPEDPEAWDIBOEWR/W
1054IE7:0RF1LERF1FERF1WERF1NERF0LERF0FERF0WERF0NER/W
15:8TEFLETEFFETEFWETEFNETFEETCFETCEHPMER/W
23:16EPEELOEBEUEBECEDRXETOOEMRAFETSWER/W
31:24ReservedARAEPEDEPEAEWDIEBOEEWER/W
1058ILS7:0RF1LLRF1FLRF1WLRF1NLRF0LLRF0FLRF0WLRF0NLR/W
15:8TEFLLTEFFLTEFWLTEFNLTFELTCFLTCLHPMLR/W
23:16EPLELOLBEULBECLDRXLTOOLMRAFLTSWLR/W
31:24ReservedARALPEDLPEALWDILBOLEWLR/W
105CILE7:0ReservedEINT1EINT0R/W
15:8ReservedR
23:16ReservedR
31:24ReservedR
1060 – 107CRSVD31:0ReservedR
1080GFC7:0ReservedANFSANFERRFSRRFERP
15:8ReservedR
23:16ReservedR
31:24ReservedR
1084SIDFC7:0FLSS[7:2] (Filter List Standard Start Address)ReservedRP
15:8FLSS[15:8] (Filter List Standard Start Address)RP
23:16LSS (List Size Standard)RP
31:24ReservedR
1088XIDFC7:0FLESA[7:2] (Filter List Extended Start Address)ReservedRP
15:8FLESA[15:8] (Filter List Extended Start Address)RP
23:16ReservedLSE (List Size Extended)RP
31:24ReservedR
108CRSVD31:0ReservedR
1090XIDAM7:0EIDM[7:0] (Extended ID AND MASK)RP
15:8EIDM[15:8] (Extended ID AND MASK)RP
23:16EIDM[23:16] (Extended ID AND MASK)RP
31:24ReservedEIDM[28:24] (Extended ID AND MASK)RP
1094HPMS7:0MSI (Message Storage Index)BIDX (Buffer Index)R
15:8FLSTFIDX (Filter Index)R
23:16ReservedR
31:24ReservedR
1098 NDAT1 7:0 ND7 ND6 ND5 ND4 ND3 ND2 ND1 ND0 R/W
15:8ND15ND14ND13ND12ND11ND10ND9ND8R/W
23:16ND23ND22ND21ND20ND19ND18ND17ND16R/W
31:24ND31ND30ND29ND28ND27ND26ND25ND24R/W
109CNDAT27:0ND39ND38ND37ND36ND35ND34ND33ND32R/W
15:8ND47ND46ND45ND44ND43ND42ND41ND40R/W
23:16ND55ND54ND53ND52ND51ND50ND49ND48R/W
31:24ND63ND62ND61ND60ND59ND58ND57ND56R/W
10A0RXF0C7:0F0SA[7:2] (RX FIFO 0 Start Address)ReservedRP
15:8F0SA[15:8] (RX FIFO 0 Start Address)RP
23:16ReservedF0S (RX FIFO 0 Size)RP
31:24F0OMF0WM (RX FIFO 0 Watermark)RP
10A4RXF0S7:0ReservedR
15:8ReservedR
23:16ReservedR
31:24ReservedR
10A8RXF0A7:0ReservedF0A (RX FIFO 0 Acknowledge Index)R/W
15:8ReservedR
23:16ReservedR
31:24ReservedR
10ACRXBC7:0RBSA[7:2] (RX Buffer Configuration)ReservedRP
15:8RBSA[15:8] (RX Buffer Configuration)RP
23:16ReservedR
31:24ReservedR
10B0RXF1C7:0F1SA[7:2] (RX FIFO 1 Start Address)ReservedRP
15:8F1SA[15:8] (RX FIFO 1 Start Address)RP
23:16ReservedF1S (RX FIFO 1 Size)RP
31:24F1OMF1WM (RX FIFO 1 Watermark)RP
10B4RXF1S7:0ReservedF1FL (RX FIFO 1 Fill Level)R
15:8ReservedF1GI (RX FIFO 1 Get Index)R
23:16ReservedF1PI (RX FIFO 1 Put Index)R
31:24DMS (Data Message Status)ReservedRF1LF1FR
10B8RXF1A7:0ReservedF1AI (RX FIFO 1 Acknowledge Index)R/W
15:8ReservedR
23:16ReservedR
31:24ReservedR
10BCRXESC7:0ReservedF1DS (RX FIFO 1 Data Field Size)ReservedF0DS (RX FIFO 0 Data Field Size)RP
15:8ReservedRBDS (RX Buffer Data Field Size)RP
23:16ReservedR
31:24ReservedR
10C0TXBC7:0TBSA[7:2] (TX Buffer Start Address)ReservedRP
15:8TBSA[15:8] (TX Buffer Start Address)RP
23:16ReservedNDTB (Number of Dedicated Transmit Buffers)RP
31:24ReservedTFQMTFQS (Transmit FIFO/Queue Size)RP
10C4TXQFS7:0ReservedTFFL (TX FIFO Free Level)R
15:8ReservedTFGI (TX FIFO Get Index)R
23:16ReservedTFQFTFQP (TX FIFO/Queue Put Index)R
31:24ReservedR
10C8TXESC7:0ReservedTBDS (TX Buffer Data Field Size)RP
15:8ReservedR
23:16ReservedR
31:24ReservedR
10CC TXBRP 7:0 TRP7 TRP6 TRP5 TRP4 TRP3 TRP2 TRP1 TRP0 R
15:8TRP15TRP14TRP13TRP12TRP11TRP10TRP9TRP8R
23:16TRP23TRP22TRP21TRP20TRP19TRP18TRP17TRP16R
31:24TRP31TRP30TRP29TRP28TRP27TRP26TRP25TRP24R
10D0TXBAR7:0AR7AR6AR5AR4AR3AR2AR1AR0R/W
15:8AR15AR14AR13AR12AR11AR10AR9AR8R/W
23:16AR23AR22AR21AR20AR19AR18AR17AR16R/W
31:24AR31AR30AR29AR28AR27AR26AR25AR24R/W
10D4TXBCR7:0CR7CR6CR5CR4CR3CR2CR1CR0RW
15:8CR15CR14CR13CR12CR11CR10CR9CR8RW
23:16CR23CR22CR21CR20CR19CR18CR17CR16RW
31:24CR31CR30CR29CR28CR27CR26CR25CR24RW
10D8TXBTO7:0TO7TO6TO5TO4TO3TO2TO1TO0R
15:8TO15TO14TO13TO12TO11TO10TO9TO8R
23:16TO23TO22TO21TO20TO19TO18TO17TO16R
31:24TO31TO30TO29TO28TO27TO26TO25TO24R
10DCTXBCF7:0CF7CF6CF5CF4CF3CF2CF1CF0R
15:8CF15CF14CF13CF12CF11CF10CF9CF8R
23:16CF23CF22CF21CF20CF19CF18CF17CF16R
31:24CF31CF30CF29CF28CF27CF26CF25CF24R
10E0TXBTIE7:0TIE7TIE6TIE5TIE4TIE3TIE2TIE1TIE0RW
15:8TIE15TIE14TIE13TIE12TIE11TIE10TIE9TIE8RW
23:16TIE23TIE22TIE21TIE20TIE19TIE18TIE17TIE16RW
31:24TIE31TIE30TIE29TIE28TIE27TIE26TIE25TIE24RW
10E4TXBCIE7:0CFIE7CFIE6CFIE5CFIE4CFIE3CFIE2CFIE1CFIE0RW
15:8CFIE15CFIE14CFIE13CFIE12CFIE11CFIE10CFIE9CFIE8RW
23:16CFIE23CFIE22CFIE21CFIE20CFIE19CFIE18CFIE17CFIE16RW
31:24CFIE31CFIE30CFIE29CFIE28CFIE27CFIE26CFIE25CFIE24RW
10E8 - 10ECRSVD31:0ReservedR
10F0TXEFC7:0EFSA[7:2] (Event FIFO Start Address)ReservedRP
15:8EFSA[15:8] (Event FIFO Start Address)RP
23:16ReservedEFS (Event FIFO Size)RP
31:24ReservedEFWM (Event FIFO Watermark)RP
10F4TXEFS7:0ReservedEFFL (Event FIFO Fill Level)
15:8ReservedEFGI (Event FIFO Get Index)
23:16ReservedEFPI (Event FIFO Put Index)
31:24ReservedTEFLEFFR
10F8TXEFA7:0ReservedEFA (Event FIFO Acknowledge Index)RW
15:8ReservedR
23:16ReservedR
31:24ReservedR
10FCRSVD31:0ReservedR