ZHCSJK5C January   2018  – October 2020 TCAN4550-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specification
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC ESD and ISO Transient Specification
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VIO Pin
      3. 8.3.3  VCCOUT Pin
      4. 8.3.4  GND
      5. 8.3.5  INH Pin
      6. 8.3.6  WAKE Pin
      7. 8.3.7  FLTR Pin
      8. 8.3.8  RST Pin
      9. 8.3.9  OSC1 and OSC2 Pins
      10. 8.3.10 nWKRQ Pin
      11. 8.3.11 nINT Interrupt Pin
      12. 8.3.12 GPIO1 Pin
      13. 8.3.13 GPO2 Pin
      14. 8.3.14 CANH and CANL Bus Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Sleep Mode
        1. 8.4.3.1 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
        2. 8.4.3.2 Local Wake Up (LWU) via WAKE Input Terminal
      4. 8.4.4 Test Mode
      5. 8.4.5 Failsafe Feature
      6. 8.4.6 Protection Features
        1. 8.4.6.1 Watchdog Function
        2. 8.4.6.2 Driver and Receiver Function
        3. 8.4.6.3 Floating Terminals
        4. 8.4.6.4 TXD_INT Dominant Timeout (DTO)
        5. 8.4.6.5 CAN Bus Short Circuit Current Limiting
        6. 8.4.6.6 Thermal Shutdown
        7. 8.4.6.7 Under Voltage Lockout (UVLO) and Unpowered Device
          1. 8.4.6.7.1 UVSUP and UVCCOUT
          2. 8.4.6.7.2 UVIO
          3. 8.4.6.7.3 Fault and M_CAN Core Behavior:
      7. 8.4.7 CAN FD
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Chip Select Not (nCS):
        2. 8.5.1.2 SPI Clock Input (SCLK):
        3. 8.5.1.3 SPI Data Input (SDI):
        4. 8.5.1.4 SPI Data Output (SDO):
      2. 8.5.2 Register Descriptions
      3.     
    6. 8.6 Register Maps
      1. 8.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F
        1. 8.6.1.1 DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]
        2. 8.6.1.2 DEVICE_ID2[31:0] (address = h0004) [reset = h30353534]
        3. 8.6.1.3 Revision (address = h0008) [reset = h00110201]
        4. 8.6.1.4 Status (address = h000C) [reset = h0000000U]
      2. 8.6.2 Device Configuration Registers: 16'h0800 to 16'h08FF
        1. 8.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]
        2. 8.6.2.2 Timestamp Prescalar (address = h0804) [reset = h00000002]
        3. 8.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]
        4. 8.6.2.4 Test Register (address = h080C) [reset = h00000000]
      3. 8.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
        1. 8.6.3.1 Interrupts (address = h0820) [reset = h00100000]
        2. 8.6.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]
        3. 8.6.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
      4. 8.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF
        1. 8.6.4.1  Core Release Register (address = h1000) [reset = hrrrddddd]
        2. 8.6.4.2  Endian Register (address = h1004) [reset = h87654321]
        3. 8.6.4.3  Customer Register (address = h1008) [reset = h00000000]
        4. 8.6.4.4  Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
        5. 8.6.4.5  Test Register (address = h1010 ) [reset = h00000000]
        6. 8.6.4.6  RAM Watchdog (address = h1014) [reset = h00000000]
        7. 8.6.4.7  Control Register (address = h1018) [reset = 0000 0019]
        8. 8.6.4.8  Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
        9. 8.6.4.9  Timestamp Counter Configuration (address = h1020) [reset = h00000000]
        10. 8.6.4.10 Timestamp Counter Value (address = h1024) [reset = h00000000]
        11. 8.6.4.11 Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]
        12. 8.6.4.12 Timeout Counter Value (address = h102C) [reset = h0000FFFF]
        13. 8.6.4.13 Reserved (address = h1030 - h103C) [reset = h00000000]
        14. 8.6.4.14 Error Counter Register (address = h1040) [reset = h00000000]
        15. 8.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]
        16. 8.6.4.16 Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]
        17. 8.6.4.17 Reserved (address = h104C) [reset = h00000000]
        18. 8.6.4.18 Interrupt Register (address = h1050) [reset = h00000000]
        19. 8.6.4.19 Interrupt Enable (address = h1054) [reset = h00000000]
        20. 8.6.4.20 Interrupt Line Select (address = h1058) [reset = h00000000]
        21. 8.6.4.21 Interrupt Line Enable (address = h105C) [reset = h00000000]
        22. 8.6.4.22 Reserved (address = h1060 - h107C) [reset = h00000000]
        23. 8.6.4.23 Global Filter Configuration (address = h1080) [reset = h00000000]
        24. 8.6.4.24 Standard ID Filter Configuration (address = h1084) [reset = h00000000]
        25. 8.6.4.25 Extended ID Filter Configuration (address = h1088) [reset = h00000000]
        26. 8.6.4.26 Reserved (address = h108C) [reset = h00000000]
        27. 8.6.4.27 Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]
        28. 8.6.4.28 High Priority Message Status (address = h1094) [reset = h00000000]
        29. 8.6.4.29 New Data 1 (address = h1098) [reset = h00000000]
        30. 8.6.4.30 New Data 2 (address = h109C) [reset = h00000000]
        31. 8.6.4.31 Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]
        32. 8.6.4.32 Rx FIFO 0 Status (address = h10A4) [reset = h00000000]
        33. 8.6.4.33 Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]
        34. 8.6.4.34 Rx Buffer Configuration (address = h10AC) [reset = h00000000]
        35. 8.6.4.35 Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]
        36. 8.6.4.36 Rx FIFO 1 Status (address = h10B4) [reset = h00000000]
        37. 8.6.4.37 Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]
        38. 8.6.4.38 Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]
        39. 8.6.4.39 Tx Buffer Configuration (address = h10C0) [reset = h00000000]
        40. 8.6.4.40 Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]
        41. 8.6.4.41 Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]
        42. 8.6.4.42 Tx Buffer Request Pending (address = h10CC) [reset = h00000000]
        43. 8.6.4.43 Tx Buffer Add Request (address = h10D0) [reset = h00000000]
          1. 8.6.4.43.1  Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]
          2. 8.6.4.43.2  Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
          3. 8.6.4.43.3  Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]
          4. 8.6.4.43.4  Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]
          5. 8.6.4.43.5  Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
          6. 8.6.4.43.6  Reserved (address = h10E8) [reset = h00000000]
          7. 8.6.4.43.7  Reserved (address = h10EC) [reset = h00000000]
          8. 8.6.4.43.8  Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]
          9. 8.6.4.43.9  Tx Event FIFO Status (address = h10F4) [reset = h00000000]
          10. 8.6.4.43.10 Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]
          11. 8.6.4.43.11 Reserved (address = h10FC) [reset = h00000000]
  9. Application and Implementation
    1. 9.1 Application Design Consideration
      1. 9.1.1 Crystal and Clock Input Requirements
      2. 9.1.2 Bus Loading, Length and Number of Nodes
      3. 9.1.3 CAN Termination
        1. 9.1.3.1 Termination
        2.      
        3. 9.1.3.2 CAN Bus Biasing
      4. 9.1.4 INH Brownout Behavior
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Requirements
      2. 9.2.2 Detailed Design Procedures
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 CAN Transceiver Physical Layer Standards:
        2. 12.1.1.2 EMC requirements:
        3. 12.1.1.3 Conformance Test requirements:
        4. 12.1.1.4 Support Documents
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Watchdog Function

The TCAN4550-Q1 contains a watchdog (WD) timeout function. When using the WD timeout function the WD runs continuously. The WD is default enabled and can be configured with four different timer values. WD is active in normal and standby modes and off in sleep mode. Once the device enters standby or normal mode the timer does not start until the first input trigger event. This event can be either writing a one to register 16'h0800[18] or if selected, by changing the voltage level on the GPIO1 pin either high or low when configured for watchdog input. If the first trigger is not set the watchdog is disabled. The first trigger can happen in standby mode or normal mode. This is system implementation specific. While the timer is running, a SPI command writing a one to 16'h0800[18] resets the WD_TIMER timer or if configured for pin control the GPIO1 behaves as the watchdog input bit.

The TCAN4550-Q1 has two ways of setting the trigger bit: via a SPI command and, if selected, through a GPI (GPIO1 configured as GPI). When a GPI pin is used any rising or falling edge resets the timer. A watchdog event can be conveyed back to the microprocessor in two methods: interrupt on nINT pin or, if selected, the GPO2 pin can be programmed to toggle upon a WD timeout. A timeout can initiate one of three actions by the TCAN4550-Q1: interrupt, INH toggle plus putting the device into standby mode or toggle watchdog output reset pin if enabled. The input CLKIN or crystal values needs to be entered into reg 16'h0800[27] and is either 20 MHz or 40MHz. See Table 8-2 for the register settings for the watchdog function.

Note:

  • If the device enters UVIO protected mode, the watchdog timer is held in reset. When the device returns to standby mode, the timer resumes counting.
  • Once the command to enter sleep mode takes place, the WD timer is turned off and does not trigger a watchdog event.
  • If the any of the watchdog registers needs to be changed, the watchdog must be disabled and the change made and then re-enabled.

Table 8-2 Watchdog Registers and Descriptions
Address BIT(S) Field Type Reset DESCRIPTION
16'h0800 29:28 WD_TIMER R/W 2'b00 WD_TIMER: Watchdog timer

00 = 60 ms

01 = 600 ms

10 = 3 s

11 = 6 s

27 CLK_REF R/W 1'b1 CLK_REF: CLKIN/Crystal frequency reference

0 = 20 MHz

1 = 40 MHz

23:22 GPO2_CONFIG R/W 2'b00 GPO2_CONFIG: GPO2 configuration

00 = No action

01 = M_CAN_INT 0 interrupt (active low)

10 = Watchdog output

11 = Mirrors nINT pin

18 WD_BIT_SET W1C 1'b0 WD_BIT_SET: write a 1 to reset timer: if times out; this bit is set and then the selected action from register 16'h0800[17:16] takes place.

Note: This is a self-clearing bit. Writing a 1 resets the timer and then the bit clears.

17:16 WD_ACTION R/W 2'b00 WD_ACTION: Selected action when WD_TIMER times out

00 = Set interrupt flag and if a pin is configure to reflect WD output as an interrupt the pin shows a low.

01 = Pulse INH pin and place device into standby mode – high - low - high ≈300ms

10 = Pulse watchdog output pin if enabled – high - low - high ≈300ms

11 = Reserved

Note: Interrupt flag is always set for a WD timeout event.

16'h0800 15:14 GPIO1_CONFIG RW 2'b01 GPIO1_CONFIG: GPIO1 Pin Function Select

00 = GPO

01 = Reserved

10 = GPI – Automatically becomes a WD input trigger pin.

11 = Reserved

3 WD_EN RXU 1'b1 WD_EN - Watchdog Enable

0 = Disable

1 = Enabled