In some applications, such as batteries with high-leakage or batteries in parallel with a system load, the battery current may never reach the ITERM threshold while in CV mode. The device offers a dedicated CV timer to control the amount of time the charger stays in absorb phase. This is especially important for lead-acid batteries, where limiting the exposure of the battery terminals to absorb voltage is ideal.

The CV timer begins counting when the device enters the absorb phase , and its duration can be programmed through the CV_TMR register bits. Note that CV_TMR = 0 disables the timer altogether. The CV timer is an absolute timer.

During faults which disable charging or when device falls out of CV regulation due to IAC_DPM or VAC_DPM, the CV timer is suspended. Once the device return to CV mode, the CV timer resumes. If the charging cycle is stopped and started again, the timer gets reset (toggle CE pin or EN_CHG bit restarts the timer).

An INT is asserted to the host when CV timer expires, and can be masked via the CV_TMR_MASK bit.