SLUSE53 December   2024 BQ25751

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics (BQ25751)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Power-On-Reset
      2. 7.3.2 Device Power-Up From Battery Without Input Source
      3. 7.3.3 Device Power Up from Input Source
        1. 7.3.3.1 VAC Operating Window Programming (ACUV and ACOV)
        2. 7.3.3.2 REGN Regulator (REGN LDO)
        3. 7.3.3.3 Switching Frequency and Synchronization (FSW_SYNC)
        4. 7.3.3.4 Device HIZ Mode
      4. 7.3.4 Battery Charging Management
        1. 7.3.4.1 Autonomous Charging Cycle
          1. 7.3.4.1.1 Charge Current Programming (ICHG pin and ICHG_REG)
        2. 7.3.4.2 Lead Acid Battery Charging Profile
        3. 7.3.4.3 Absorb Charge to Float Charge for Lead-Acid
        4. 7.3.4.4 CV Timer
        5. 7.3.4.5 Thermistor Qualification
          1. 7.3.4.5.1 Temperature Compensated Charging
          2. 7.3.4.5.2 Cold/Hot Temperature Window in Reverse Mode
      5. 7.3.5 Power Path Management
        1. 7.3.5.1 Dynamic Power Management: Input Voltage and Input Current Regulation
          1. 7.3.5.1.1 Input Current Regulation
            1. 7.3.5.1.1.1 ILIM_HIZ Pin
          2. 7.3.5.1.2 Input Voltage Regulation
            1. 7.3.5.1.2.1 Max Power Point Tracking (MPPT) for Solar PV Panel
      6. 7.3.6 Reverse Mode Power Direction
        1. 7.3.6.1 Auto Reverse Mode
      7. 7.3.7 Integrated 16-Bit ADC for Monitoring
      8. 7.3.8 Status Outputs (PG, STAT1, STAT2, and INT)
        1. 7.3.8.1 Power Good Indicator (PG)
        2. 7.3.8.2 Charging Status Indicator (STAT1, STAT2 Pins)
        3. 7.3.8.3 Interrupt to Host (INT)
      9. 7.3.9 Serial Interface
        1. 7.3.9.1 Data Validity
        2. 7.3.9.2 START and STOP Conditions
        3. 7.3.9.3 Byte Format
        4. 7.3.9.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.3.9.5 Target Address and Data Direction Bit
        6. 7.3.9.6 Single Write and Read
        7. 7.3.9.7 Multi-Write and Multi-Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 BQ25751 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application (Standalone)
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ACUV / ACOV Input Voltage Operating Window Programming
          2. 8.2.1.2.2 Charge Voltage Selection
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Inductor Selection
          5. 8.2.1.2.5 Input (VAC / SYS) Capacitor
          6. 8.2.1.2.6 Output (VBAT) Capacitor
          7. 8.2.1.2.7 Sense Resistor (RAC_SNS and RBAT_SNS) and Current Programming
          8. 8.2.1.2.8 ACFETs and BATFETs Selection
          9. 8.2.1.2.9 Converter Fast Transient Response
        3. 8.2.1.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tape and Reel Information
    3. 13.3 Mechanical Data

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RRV|36
散热焊盘机械数据 (封装 | 引脚)

7.3.4.1 Autonomous Charging Cycle

When battery charging is enabled (EN_CHG bit =1 and CE pin is LOW), the device autonomously completes a charging cycle without host involvement. The device charging parameters can be set by hardware through the FB pin to set regulation voltage and the ICHG pin to set charging current. The host can always control the charging operation and optimize the charging parameters by writing to the corresponding registers through I2C.

Table 7-2 Lead Acid Charging Parameter Default Settings
DEFAULT MODE BQ25751
Charge Stages Fast Charge (CC) → Absorb Charge → Float Charge
FB Voltage Regulation Target (VFB_REG) - Float Voltage 1.536 V
Absorb Voltage 109.1% x VFB_REG = 1.6758 V
Charging Current ICHG
Termination Current 10% x ICHG
CV Timer 5 hr
NTC Temperature Float Voltage Compensation (at battery) -3mV/°C/cell
(1-cell = ~2.2 V)
Safety Timer Disabled

A new charge cycle starts when the following conditions are valid:

  • VAC is within the ACUV and ACOV operating window
  • Device is not in HIZ mode (EN_HIZ = 0 and ILIM_HIZ pin voltage is below VIH_ILIM_HIZ)
  • REGN is above VREGN_OK
  • Battery charging is enabled (EN_CHG = 1 and CE pin is LOW )
  • No thermistor fault on TS
  • No safety timer fault

For lead acid battery charging (EN_3_STAGE_CHARGE = 1), the charger device automatically transitions from Absorb phase to Float voltage phase when the charging current is below termination threshold, and device is not in DPM mode. In addition, the device offers a dedicated CV timer to transition from Absorb to Float stage after a programmable period (CV_TMR bits) regardless of the charge current value. The device remains in the Float stage indefinitely. A new charge cycle can be initiated by toggle of either CE pin or EN_CHG bit.

The status register (CHARGE_STAT) indicates the different charging phases as:

  • 000 – Not Charging
  • 011 – Fast-charge (CC mode)
  • 100 – Absorb Charge (CV mode)
  • 101 – Float Charge (CV mode)
  • 110 – Top-off Timer Active Charging
  • All other codes are RESERVED

When the charger transitions to any of these states, including when charge cycle is completed, an INT pulse is asserted to notify the host.

For supercapacitor charging, the charger outputs ICHG current as long as the feedback voltage (VFB) is below VFB_REG. The following settings are recommended for supercapacitor charging:

  • EN_TERM = 0