ZHCSH81 December   2017 PGA302

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      PGA302 简化框图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Overvoltage and Reverse Voltage Protection
    6. 7.6  Linear Regulators
    7. 7.7  Internal Reference
    8. 7.8  Internal Oscillator
    9. 7.9  Bridge Sensor Supply
    10. 7.10 Temperature Sensor Supply
    11. 7.11 Bridge Offset Cancel
    12. 7.12 P Gain and T Gain Input Amplifiers (Chopper Stabilized)
    13. 7.13 Analog-to-Digital Converter
    14. 7.14 Internal Temperature Sensor
    15. 7.15 Bridge Current Measurement
    16. 7.16 One Wire Interface
    17. 7.17 DAC Output
    18. 7.18 DAC Gain for DAC Output
    19. 7.19 Non-Volatile Memory
    20. 7.20 Diagnostics - PGA30x
    21. 7.21 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Overvoltage and Reverse Voltage Protection
      2. 8.3.2  Linear Regulators
      3. 8.3.3  Internal Reference
      4. 8.3.4  Internal Oscillator
      5. 8.3.5  VBRGP and VBRGN Supply for Resistive Bridge
      6. 8.3.6  ITEMP Supply for Temperature Sensor
      7. 8.3.7  P Gain
      8. 8.3.8  T Gain
      9. 8.3.9  Bridge Offset Cancel
      10. 8.3.10 Analog-to-Digital Converter
        1. 8.3.10.1 Sigma Delta Modulator for ADC
        2. 8.3.10.2 Decimation Filter for ADC
        3. 8.3.10.3 Internal Temperature Sensor ADC Conversion
        4. 8.3.10.4 ADC Scan Mode
          1. 8.3.10.4.1 P-T Multiplexer Timing in Auto Scan Mode
      11. 8.3.11 Internal Temperature Sensor
      12. 8.3.12 Bridge Current Measurement
      13. 8.3.13 Digital Interface
      14. 8.3.14 OWI
        1. 8.3.14.1 Overview of OWI Interface
        2. 8.3.14.2 Activating and Deactivating the OWI Interface
          1. 8.3.14.2.1 Activating OWI Communication
          2. 8.3.14.2.2 Deactivating OWI Communication
        3. 8.3.14.3 OWI Protocol
          1. 8.3.14.3.1 OWI Frame Structure
            1. 8.3.14.3.1.1 Standard field structure:
            2. 8.3.14.3.1.2 Frame Structure
            3. 8.3.14.3.1.3 Sync Field
            4. 8.3.14.3.1.4 Command Field
            5. 8.3.14.3.1.5 Data Field(s)
          2. 8.3.14.3.2 OWI Commands
            1. 8.3.14.3.2.1 OWI Write Command
            2. 8.3.14.3.2.2 OWI Read Initialization Command
            3. 8.3.14.3.2.3 OWI Read Response Command
            4. 8.3.14.3.2.4 OWI Burst Write Command (EEPROM Cache Access)
            5. 8.3.14.3.2.5 OWI Burst Read Command (EEPROM Cache Access)
          3. 8.3.14.3.3 OWI Operations
            1. 8.3.14.3.3.1 Write Operation
            2. 8.3.14.3.3.2 Read Operation
            3. 8.3.14.3.3.3 EEPROM Burst Write
            4. 8.3.14.3.3.4 EEPROM Burst Read
        4. 8.3.14.4 OWI Communication Error Status
      15. 8.3.15 I2C Interface
        1. 8.3.15.1 Overview of I2C Interface
        2. 8.3.15.2 I2C Interface Protocol
        3. 8.3.15.3 Clocking Details of I2C Interface
      16. 8.3.16 DAC Output
      17. 8.3.17 DAC Gain for DAC Output
        1. 8.3.17.1 Connecting DAC Output to DAC GAIN Input
      18. 8.3.18 Memory
        1. 8.3.18.1 EEPROM Memory
          1. 8.3.18.1.1 EEPROM Cache
          2. 8.3.18.1.2 EEPROM Programming Procedure
          3. 8.3.18.1.3 EEPROM Programming Current
          4. 8.3.18.1.4 CRC
      19. 8.3.19 Diagnostics
        1. 8.3.19.1 Power Supply Diagnostics
        2. 8.3.19.2 Sensor Connectivity/Gain Input Faults
        3. 8.3.19.3 Gain Output Diagnostics
        4. 8.3.19.4 PGA302 Harness Open Wire Diagnostics
        5. 8.3.19.5 EEPROM CRC and TRIM Error
      20. 8.3.20 Digital Compensation and Filter
        1. 8.3.20.1 Digital Gain and Offset
        2. 8.3.20.2 TC and NL Correction
        3. 8.3.20.3 Clamping
        4. 8.3.20.4 Filter
      21. 8.3.21 Revision ID
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 Programmer's Model
        1. 8.5.1.1 Memory Map
        2. 8.5.1.2 Control and Status Registers
          1. 8.5.1.2.1  MICRO_INTERFACE_CONTROL (DI Page Address = 0x0) (DI Page Offset = 0x0C)
            1. Table 11. MICRO_INTERFACE_CONTROL Register Field Descriptions
          2. 8.5.1.2.2  PSMON1 (M0 Address= 0x40000558) (DI Page Address = 0x2) (DI Page Offset = 0x58)
            1. Table 12. PSMON1 Register Field Descriptions
          3. 8.5.1.2.3  AFEDIAG (M0 Address= 0x4000055A) (DI Page Address = 0x2) (DI Page Offset = 0x5A)
            1. Table 13. AFEDIAG Register Field Descriptions
          4. 8.5.1.2.4  P_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x47)
            1. Table 14. P_GAIN_SELECT Register Field Descriptions
          5. 8.5.1.2.5  T_GAIN_SELECT (DI Page Address = 0x2) (DI Page Offset = 0x48)
            1. Table 15. T_GAIN_SELECT Register Field Descriptions
          6. 8.5.1.2.6  TEMP_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x4C)
            1. Table 16. TEMP_CTRL Register Field Descriptions
          7. 8.5.1.2.7  OFFSET_CANCEL (DI Page Address = 0x2) (DI Page Offset = 0x4E)
            1. Table 17. OFFSET_CANCEL Register Field Descriptions
          8. 8.5.1.2.8  PADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x10)
            1. Table 18. PADC_DATA1 Register Field Descriptions
          9. 8.5.1.2.9  PADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x11)
            1. Table 19. PADC_DATA2 Register Field Descriptions
          10. 8.5.1.2.10 TADC_DATA1 (DI Page Address = 0x0) (DI Page Offset = 0x14)
            1. Table 20. TADC_DATA1 Register Field Descriptions
          11. 8.5.1.2.11 TADC_DATA2 (DI Page Address = 0x0) (DI Page Offset = 0x15)
            1. Table 21. TADC_DATA2 Register Field Descriptions
          12. 8.5.1.2.12 DAC_REG0_1 (DI Page Address = 0x2) (DI Page Offset = 0x30)
            1. Table 22. DAC_REG0_1 Register Field Descriptions
          13. 8.5.1.2.13 DAC_REG0_2 (DI Page Address = 0x2) (DI Page Offset = 0x31)
            1. Table 23. DAC_REG0_2 Register Field Descriptions
          14. 8.5.1.2.14 OP_STAGE_CTRL (DI Page Address = 0x2) (DI Page Offset = 0x3B)
            1. Table 24. OP_STAGE_CTRL Register Field Descriptions
          15. 8.5.1.2.15 EEPROM_ARRAY (DI Page Address = 0x5) (DI Page Offset = 0x00 - 0x7F)
            1. Table 25. EEPROM_ARRAY Register Range Descriptions
          16. 8.5.1.2.16 EEPROM_CACHE_BYTE0 (DI Page Address = 0x5) (DI Page Offset = 0x80)
            1. Table 26. EEPROM_CACHE_BYTE0 Register Field Descriptions
          17. 8.5.1.2.17 EEPROM_CACHE_BYTE1 (DI Page Address = 0x5) (DI Page Offset = 0x81)
            1. Table 27. EEPROM_CACHE_BYTE1 Register Field Descriptions
          18. 8.5.1.2.18 EEPROM_PAGE_ADDRESS (DI Page Address = 0x5) (DI Page Offset = 0x82)
            1. Table 28. EEPROM_PAGE_ADDRESS Register Field Descriptions
          19. 8.5.1.2.19 EEPROM_CTRL (DI Page Address = 0x5) (DI Page Offset = 0x83)
            1. Table 29. EEPROM_CTRL Register Field Descriptions
          20. 8.5.1.2.20 EEPROM_CRC (DI Page Address = 0x5) (DI Page Offset = 0x84)
            1. Table 30. EEPROM_CRC Register Field Descriptions
          21. 8.5.1.2.21 EEPROM_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x85)
            1. Table 31. EEPROM_STATUS Register Field Descriptions
          22. 8.5.1.2.22 EEPROM_CRC_STATUS (DI Page Address = 0x5) (DI Page Offset = 0x86)
            1. Table 32. EEPROM_CRC_STATUS Register Field Descriptions
          23. 8.5.1.2.23 EEPROM_CRC_VALUE (DI Page Address = 0x5) (DI Page Offset = 0x87)
            1. Table 33. EEPROM_CRC_VALUE Register Field Descriptions
          24. 8.5.1.2.24 H0 (EEPROM Address= 0x40000000)
            1. Table 34. H0 Register Field Descriptions
          25. 8.5.1.2.25 H1 (EEPROM Address= 0x40000002)
            1. Table 35. H1 Register Field Descriptions
          26. 8.5.1.2.26 H2 (EEPROM Address= 0x40000004)
            1. Table 36. H2 Register Field Descriptions
          27. 8.5.1.2.27 H3 (EEPROM Address= 0x40000006)
            1. Table 37. H3 Register Field Descriptions
          28. 8.5.1.2.28 G0 (EEPROM Address= 0x40000008)
            1. Table 38. G0 Register Field Descriptions
          29. 8.5.1.2.29 G1 (EEPROM Address= 0x4000000A)
            1. Table 39. G1 Register Field Descriptions
          30. 8.5.1.2.30 G2 (EEPROM Address= 0x4000000C)
            1. Table 40. G2 Register Field Descriptions
          31. 8.5.1.2.31 G3 (EEPROM Address= 0x4000000E)
            1. Table 41. G3 Register Field Descriptions
          32. 8.5.1.2.32 N0 (EEPROM Address= 0x40000010)
            1. Table 42. N0 Register Field Descriptions
          33. 8.5.1.2.33 N1 (EEPROM Address= 0x40000012)
            1. Table 43. N1 Register Field Descriptions
          34. 8.5.1.2.34 N2 (EEPROM Address= 0x40000014)
            1. Table 44. N2 Register Field Descriptions
          35. 8.5.1.2.35 N3 (EEPROM Address= 0x40000016)
            1. Table 45. N3 Register Field Descriptions
          36. 8.5.1.2.36 M0 (EEPROM Address= 0x40000018)
            1. Table 46. M0 Register Field Descriptions
          37. 8.5.1.2.37 M1 (EEPROM Address= 0x4000001A)
            1. Table 47. M1 Register Field Descriptions
          38. 8.5.1.2.38 M2 (EEPROM Address= 0x4000001C)
            1. Table 48. M2 Register Field Descriptions
          39. 8.5.1.2.39 M3 (EEPROM Address= 0x4000001E)
            1. Table 49. M3 Register Field Descriptions
          40. 8.5.1.2.40 PADC_GAIN (EEPROM Address= 0x40000020)
            1. Table 50. PADC_GAIN Register Field Descriptions
          41. 8.5.1.2.41 TADC_GAIN (EEPROM Address= 0x40000021)
            1. Table 51. TADC_GAIN Register Field Descriptions
          42. 8.5.1.2.42 PADC_OFFSET (EEPROM Address= 0x40000022)
            1. Table 52. PADC_OFFSET Register Field Descriptions
          43. 8.5.1.2.43 TADC_OFFSET (EEPROM Address= 0x40000024)
            1. Table 53. TADC_OFFSET Register Field Descriptions
          44. 8.5.1.2.44 TEMP_SW_CTRL (EEPROM Address= 0x40000028)
            1. Table 54. TEMP_SW_CTRL Register Field Descriptions
          45. 8.5.1.2.45 DAC_FAULT_MSB (EEPROM Address= 0x4000002A)
            1. Table 55. DAC_FAULT_MSB Register Field Descriptions
          46. 8.5.1.2.46 LPF_A0_MSB (EEPROM Address= 0x4000002B)
            1. Table 56. LPF_A0_MSB Register Field Descriptions
          47. 8.5.1.2.47 LPF_A1 (EEPROM Address= 0x4000002C)
            1. Table 57. A1 Register Field Descriptions
          48. 8.5.1.2.48 LPF_A2 (EEPROM Address= 0x4000002E)
            1. Table 58. A2 Register Field Descriptions
          49. 8.5.1.2.49 .LPF_B1 (EEPROM Address= 0x40000030)
            1. Table 59. B1 Register Field Descriptions
          50. 8.5.1.2.50 NORMAL_LOW (EEPROM Address= 0x40000032)
            1. Table 60. NORMAL_LOW Register Field Descriptions
          51. 8.5.1.2.51 NORMAL_HIGH (EEPROM Address= 0x40000034)
            1. Table 61. NORMAL_HIGH Register Field Descriptions
          52. 8.5.1.2.52 LOW_CLAMP (EEPROM Address= 0x40000036)
            1. Table 62. LOW_CLAMP Register Field Descriptions
          53. 8.5.1.2.53 HIGH_CLAMP (EEPROM Address= 0x40000038)
            1. Table 63. HIGH_CLAMP Register Field Descriptions
          54. 8.5.1.2.54 DIAG_BIT_EN (EEPROM Address= 0x4000003A)
            1. Table 64. DIAG_BIT_EN Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 0-5V Voltage Output
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Data
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.5.1.2 Control and Status Registers

Table 10. PGA302 Control and Status Registers

Register NameDI Page AddressDI Offset AddressEEPROM AddressR/WD7D6D5D4D3D2D1D0
H0_LSB N/A N/A 0x40000000 RW H0 [7:0]
H0_MSB N/A N/A 0x40000001 RW H0 [15:8]
H1_LSB N/A N/A 0x40000002 RW H1 [7:0]
H1_MSB N/A N/A 0x40000003 RW H1 [15:8]
H2_LSB N/A N/A 0x40000004 RW H2 [7:0]
H2_MSB N/A N/A 0x40000005 RW H2 [15:8]
H3_LSB N/A N/A 0x40000006 RW H3 [7:0]
H3_MSB N/A N/A 0x40000007 RW H3 [15:8]
G0_LSB N/A N/A 0x40000008 RW G0 [7:0]
G0_MSB N/A N/A 0x40000009 RW G0 [15:8]
G1_LSB N/A N/A 0x4000000A RW G1 [7:0]
G1_MSB N/A N/A 0x4000000B RW G1 [15:8]
G2_LSB N/A N/A 0x4000000C RW G2 [7:0]
G2_MSB N/A N/A 0x4000000D RW G2 [15:8]
G3_LSB N/A N/A 0x4000003E RW G3 [7:0]
G3_MSB N/A N/A 0x4000003F RW G3 [15:8]
N0_LSB N/A N/A 0x40000010 RW N0 [7:0]
N0_MSB N/A N/A 0x40000011 RW N0 [15:8]
N1_LSB N/A N/A 0x40000012 RW N1 [7:0]
N1_MSB N/A N/A 0x40000013 RW N1 [15:8]
N2_LSB N/A N/A 0x40000014 RW N2 [7:0]
N2_MSB N/A N/A 0x40000015 RW N2 [15:8]
N3_LSB N/A N/A 0x40000016 RW N3 [7:0]
N3_MSB N/A N/A 0x40000017 RW N3 [15:8]
M0_LSB N/A N/A 0x40000018 RW M0 [7:0]
M0_MSB N/A N/A 0x40000019 RW M0 [15:8]
M1_MSB N/A N/A 0x4000001A RW M1 [7:0]
M1_LSB N/A N/A 0x4000001B RW M1 [15:8]
M2_LSB N/A N/A 0x4000001C RW M2 [7:0]
M2_MSB N/A N/A 0x4000001D RW M2 [15:8]
M3_LSB N/A N/A 0x4000001E RW M3 [7:0]
M3_MSB N/A N/A 0x4000001F RW M3 [15:8]
PADC_GAIN N/A N/A 0x40000020 RW PADC_GAIN [7:0]
TADC_GAIN N/A N/A 0x40000021 RW TADC_GAIN [7:0]
PADC_OFFSET_BYTE0 N/A N/A 0x40000022 RW PADC_OFFSET [7:0]
PADC_OFFSET_BYTE1 N/A N/A 0x40000023 RW PADC_OFFSET [15:8]
TADC_OFFSET_BYTE0 N/A N/A 0x40000024 RW TADC_OFFSET [7:0]
TADC_OFFSET_BYTE1 N/A N/A 0x40000025 RW TADC_OFFSET [15:8]
P_GAIN_
SELECT 		0x2 0x47 0x40000026 RW P_INV P_MUX_
CTRL[1]		 P_MUX_
CTRL[0]		 PSEM P_GAIN[2] P_GAIN[1] P_GAIN[0]
T_GAIN_
SELECT 		0x2 0x48 0x40000027 RW T_INV Write 0 T_MUX_
CTRL[1]		 T_MUX_
CTRL[0]		 TSEM T_GAIN[2] T_GAIN[1] T_GAIN[0]
TEMP_CTRL 0x2 0x4C N/A RW Write 0 ITEMP_
CTRL[2] 		ITEMP_
CTRL[1] 		ITEMP_
CTRL[0]
TEMP_SW_CTRL N/A N/A 0x40000028 RW Write 0 ITEMP_
CTRL[2] 		ITEMP_
CTRL[1] 		ITEMP_
CTRL[0] 		OFFSET_EN DIAG_ENABLE DACCAP_EN EEPROM_LOCK
OFFSET_CANCEL 0x2 0x4E 0x40000029 RW Write 0 OFFSET_
CANCEL_VAL[4]		 OFFSET
CANCEL_VAL[3]		 OFFSET
CANCEL_VAL[2]		 OFFSET
CANCEL_VAL[1]		 OFFSET
CANCEL_VAL[0]
DAC_FAULT_MSB N/A N/A 0x4000002A RW DAC_FAULT[15:8]
LPF_A0_MSB N/A N/A 0x4000002B RW A0 [15:8]
LPF_A1_LSB N/A N/A 0x4000002C RW A1 [7:0]
LPF_A1_MSB N/A N/A 0x4000002D RW A1 [15:8]
LPF_A2_LSB N/A N/A 0x4000002E RW A2 [7:0]
LPF_A2_MSB N/A N/A 0x4000002F RW A2 [15:8]
LPF_B1_LSB N/A N/A 0x40000030 RW B1 [7:0]
LPF_B1_MSB N/A N/A 0x40000031 RW B1 [15:8]
PADC_DATA1 0x2 0x20 N/A R PADC_DATA [7:0]
PADC_DATA2 0x2 0x21 N/A R PADC_DATA [15:8]
TADC_DATA1 0x2 0x24 N/A R TADC_DATA [7:0]
TADC_DATA2 0x2 0x25 N/A R TADC_DATA [15:8]
DAC_REG0_1 0x2 0x30 N/A RW DAC_VALUE [7:0]
DAC_REG0_2 0x2 0x31 N/A RW DAC_VALUE [11:8]
OP_STAGE_CTRL 0x2 0x3B N/A RW DACCAP_EN
NORMAL_LOW_LSB N/A N/A 0x40000032 RW NORMAL_DAC_LOW [7:0]
NORMAL_LOW_MSB N/A N/A 0x40000033 RW NORMAL_DAC_LOW [11:8]
NORMAL_HIGH_LSB N/A N/A 0x40000034 RW NORMAL_DAC_HIGH [7:0]
NORMAL_HIGH_MSB N/A N/A 0x40000035 RW NORMAL_DAC_HIGH [11:8]
LOW_CLAMP_LSB N/A N/A 0x40000036 RW CLAMP_DAC_LOW [7:0]
LOW_CLAMP_MSB N/A N/A 0x40000037 RW CLAMP_DAC_LOW [11:8]
HIGH_CLAMP_LSB N/A N/A 0x40000038 RW CLAMP_DAC_HIGH [7:0]
HIGH_CLAMP_MSB N/A N/A 0x40000039 RW CLAMP_DAC_HIGH [11:8]
DIAG_BIT_EN N/A N/A 0x4000003A RW TGAIN_UV_EN TGAIN_OV_EN PGAIN_UV_EN PGAIN_OV_EN VINT_OV_EN VINP_UV_EN VINP_OV_EN
PSMON1 0x2 0x58 N/A RW DVDD_OV REF_UV REF_OV VBRG_UV VBRG_OV
AFEDIAG 0x2 0x5A N/A RW TGAIN_UV TGAIN_OV PGAIN_UV PGAIN_OV VINT_OV VINP_UV VINP_OV
SERIAL_NUMBER_BYTE0 N/A N/A 0x4000003B RW SERIAL_NUMBER [7:0]
SERIAL_NUMBER_BYTE1 N/A N/A 0x4000003C RW SERIAL_NUMBER [15:8]
SERIAL_NUMBER_BYTE2 N/A N/A 0x4000003D RW SERIAL_NUMBER [23:16]
SERIAL_NUMBER_BYTE3 N/A N/A 0x4000003E RW SERIAL_NUMBER [31:24]
USER_FREE_SPACE N/A N/A 0x4000003F-
0x4000007E		 RW
EEPROM_CRC N/A N/A 0x4000007F RW EEPROM_CRC [7:0]
MICRO_
INTERFACE_
CONTROL		 0x0 0x0C N/A RW MICRO_RESET IF_SEL
EEPROM ARRAY 0x5 0x00-0x7F N/A R
EEPROM_CACHE 0x5 0x80-0x81 N/A RW
EEPROM_PAGE_
ADDRESS		 0x5 0x82 N/A RW ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
EEPROM_CTRL 0x5 0x83 N/A RW Write 0 ERASE PROGRAM
EEPROM_CRC 0x5 0x84 N/A RW CALCULATE
_CRC
EEPROM_STATUS 0x5 0x85 N/A R PROGRAM_IN
_PROGRESS		 ERASE_IN
_PROGRESS		 READ_IN
_PROGRESS
EEPROM_CRC
_STATUS		 0x5 0x86 N/A R CRC_GOOD CRC_CHECK
_IN_PROG
EEPROM_CRC
_VALUE		 0x5 0x87 N/A R EEPROM_CRC_VALUE [7:0]