ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The PLL1_CALCTRL1 register is described in the following table.
Bit # | Field | Type | Reset | EEPROM | Description |
---|---|---|---|---|---|
[7:1] | RESERVED | - | - | N | Reserved. |
[0] | PLL1_LOOPBW | RW | 0 | Y | PLL1 Loop bandwidth Control. When PLL1_LOOPBW is 1 the loop bandwidth of PLL1 is reduced to 200 Hz (jitter cleaner mode). When PLL1_LOOPBW is 0 the loop bandwidth of PLL1 is set to its normal range (clock generator mode). NOTE: Proper PLL1 settings must be used (PFD, charge pump, loop filter) with setting the desired value for PLL1_LOOPBW. |