ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
For this example, when using the WEBENCH Clock Architect Tool, the reference would have been manually entered as 25 MHz according to input frequency requirements. Enter the desired output frequencies and click on 'Generate Solutions'. Select LMK03328 from the solution list.
From the simulation page of the WEBENCH Clock Architect Tool, it can be seen that to maximize phase detector frequencies, PLL1 and PLL2 R and M dividers are set to 1, doublers are enabled and N1 divider is set to 200 and N2 divider is set to 192. This results in a VCO1 frequency of 5 GHz and VCO2 frequency of 4.8 GHz. The tool also tries to select maximum possible value for the PLL post dividers and for this example, the post divider for each PLL is set to 8. At this point the design meets all input and output frequency requirements and it is possible to design a loop filter for system and simulate performance on the clock outputs. However, consider also the following: