11.2.4.1.4 PLL and Clock Output Assignment
At this time the WEBENCH Clock Architect Tool does not assign output frequencies to specific output ports on the device with the intention to minimize cross-coupled spurs and jitter. The user may wish to make some educated re-assignment of outputs when using the EVM programming tool to configure the device registers appropriately.
In an effort to optimize device configuration for best jitter performance, consider the following guidelines:
- Because the clock outputs, intended to be used to clock high-data rates, are required with the lowest possible jitter, it is best to assign 156.25 MHz to outputs 0 and 1 and assign 125 MHz to outputs 2 and 3.
- To minimize cross coupling between PLLs, select PLL2 VCO to operate at 5 GHz and PLL1 VCO to operate 4.8 GHz.
- Coupling between outputs at different frequencies appear as spurs at offsets that is at the frequency difference between the outputs and its harmonics. Typical SerDes reference clocks need to have low integrated jitter up to an offset of 20 MHz and thus, to minimize cross coupling between output 3 and output 4, it is best to assign 100 MHz to outputs 4 and 5.
- The 133.3333 MHz can then be assigned to output 6.
- The 1.8-V LVCMOS clock at 66.6667 MHz is assigned to output 7 and it is best to select complementary LVCMOS operation. This helps to minimize coupling from this output channel to other outputs.