ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The STAT1_INT register provides control of the STATUS1 output. The STATUS1 pin is also used for test and diagnostic functions. The test configuration registers override the STAT0 register.
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7:4] | STAT1_SEL[3:0] | RW | 0x2 | Y | STATUS1 Indicator Signal Select. The STAT1_SEL field determines what information is presented on the STATUS1 output as follows. | |
STAT1CFG | STATUS1 Information | |||||
0 (0x0) | PRIREF Loss of Signal (LOS) | |||||
1 (0x1) | SECREF Loss of Signal (LOS) | |||||
2 (0x2) | PLL1 Loss of Lock (LOL) | |||||
3 (0x3) | PLL1 R Divider, divided by 2 (when R Divider is not bypassed) | |||||
4 (0x4) | PLL1 N Divider, divided by 2 | |||||
5 (0x5) | PLL2 Loss of Lock (LOL) | |||||
6 (0x6) | PLL2 R Divider, divided by 2 (when R Divider is not bypassed) | |||||
7 (0x7) | PLL2 N Divider, divided by 2 | |||||
8 (0x8) | PLL1 VCO Calibration Active (CAL) | |||||
9 (0x9) | PLL2 VCO Calibration Active (CAL) | |||||
10 (0xA) | Interrupt (INTR) | |||||
11 (0xB) | PLL1 M Divider, divided by 2 (when M Divider is not bypassed) | |||||
12 (0xC) | PLL2 M Divider, divided by 2 (when M Divider is not bypassed) | |||||
13 (0xD) | EEPROM Active | |||||
14 (0xE) | PLL1 Secondary to Primary Switch in Automatic Mode | |||||
15 (0xF) | PLL2 Secondary to Primary Switch in Automatic Mode | |||||
The polarity of STATUS1 is set by the STAT1POL bit. | ||||||
[3] | STAT1_POL | RW | 1 | Y | STATUS1 Output Polarity. The STAT1_POL bit defines the polarity of information presented on the STATUS1 output. If STAT1_POL is set to 1 then STATUS1 is active high, if STAT1_POL is 0 then STATUS1 is active low. | |
[2:0] | RESERVED | - | - | N | Reserved. |