ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The input (M) divider is a continuous 5-b counter that is present after the smart input MUX of each PLL. The output of the M divider sets the PFD frequency to the PLL and should be in the range of 1 MHz to 150 MHz. The M divider is programmed in R53 for PLL1 and R55 for PLL2.