ZHCSE36D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The 12-bit N integer divider value for PLL2 is set by the PLL2_NDIV_BY1 and PLL2_NDIV_BY0 registers.
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7:4] | RESERVED | - | - | N | Reserved. | |
[3:0] | PLL2_NDIV[11:8] | RW | 0x0 | Y | PLL2 N Divider Byte 1. PLL2 Integer N Divider bits 11 to 8. | |
PLL2_NDIV | DIVIDER RATIO | |||||
0 (0x000) | 1 | |||||
1 (0x001) | 1 | |||||
... | ... | |||||
4095 (0xFFF) | 4095 |