ZHCSK66C January 2014 – August 2019 ADS1283
PRODUCTION DATA.
The ADS1283 is a high-performance analog-to-digital converter (ADC) intended for energy exploration, seismic monitoring, chromatography, and other exacting performance applications. The converter provides 31-bit resolution in data rates from 250 SPS to 4000 SPS. See the Functional Block Diagram section for a block diagram of the ADS1283.
The ADS1283A device is functionally equivalent to the ADS1283, except that the ADS1283A supports PGA gains of 1, 4, and 16 only. The ADS1283A also relaxes the THD specification of these gains. See the Electrical Characteristics section for more details. The ADS1283B provides equivalent performance to the ADS1283, but provides two offset voltage options, 75 mV and 100 mV. See Offset for details.
The two-channel input mux allows five configurations:
See the Analog Inputs and Multiplexer section for more details.
The input mux is followed by a continuous-time PGA, featuring very low noise of 5 nV/√Hz. The PGA is controlled by register settings, allowing gains from 1 to 64 for the ADS1283 and ADS1283B, and gains of 1, 4, and 16 for the ADS1283A.
The inherently-stable, fourth-order, delta-sigma modulator measures the differential input signal
(VIN = AINP – AINN) against the differential reference (VREF = VREFP – VREFN). A digital output (MFLAG) indicates that the modulator is in overload as a result of an overdrive condition. The modulator connects to the on-chip digital filter that provides the output codes.
The digital filter consists of a variable decimation rate, fifth-order sinc filter, followed by a variable phase, decimate-by-32, finite-impulse response (FIR) low-pass filter with programmable phase, and then by an adjustable high-pass filter for dc removal of the output code. The output of the digital filter can be taken from the sinc or the FIR low-pass, with the FIR option of the infinite impulse response (IIR) high-pass section.
Gain and offset registers scale the digital filter output to produce the final code value. The scaling feature can be used for calibration and sensor gain matching.
The SYNC input resets the operation of both the digital filter and the modulator, allowing synchronization conversions of multiple ADS1283 devices to an external event. The SYNC input supports a continuously-toggled input mode that accepts an external data frame clock locked to the conversion rate.
The RESET input resets the register settings and also restarts the conversion process.
The PWDN input sets the device into a micro-power state. Note that register settings are not retained in PWDN mode. Use the STANDBY command in its place if it is desired to retain register settings (the quiescent current in standby mode is slightly higher).
Noise-immune Schmitt-trigger and clock-qualified inputs (RESET and SYNC) provide increased reliability in high-noise environments. The SPI™-compatible serial interface is used to read conversion data, in addition to reading from and writing to the configuration registers.
The device allows either unipolar and bipolar analog power-supply operation. The analog supplies may be set to +5 V for unipolar signals (with the inputs level shifted externally), or set to ±2.5 V to accept true bipolar input signals (ground referenced). The digital supply is separate and accepts voltages from 1.8 V to 3.3 V, independent of the analog power supplies used.
An internal subregulator is used to supply the digital core from DVDD. BYPAS (pin 28), is the subregulator output and requires a 1-μF capacitor for noise reduction. Note that the regulated output voltage on BYPAS is not available to drive external circuitry.