SWRU612B December 2023 – June 2026 CC3300 , CC3300MOD , CC3301 , CC3301MOD , CC3351 , CC3351MOD
Figure 2-7 SDIO Default Input Timing
Figure 2-8 SDIO Default Output Timing| Parameter | Description | MIN | MAX | Unit |
|---|---|---|---|---|
| fclock | Clock frequency, CLK | 26 | MHz | |
| tHigh | High period | 10 | ns | |
| tLow | Low period | 10 | ||
| tTLH | Rise time, CLK | 10 | ||
| tTHL | Fall time, CLK | 10 | ||
| tISU | Setup time, input valid before CLK ↑ | 5 | ||
| tIH | Hold time, input valid after CLK ↑ | 5 | ||
| tODLY | Delay time, CLK ↓ to output valid | 2 | 14 | |
| CL | Capacitive load on outputs | 15 | 40 | pF |