SWRU612B December   2023  – June 2026 CC3300 , CC3300MOD , CC3301 , CC3301MOD , CC3351 , CC3351MOD

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations – CC33xx Devices
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
      2. 2.2.2 Boot Sequence
        1. 2.2.2.1 SOP Modes
      3. 2.2.3 Power Down Sequence
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 Reset
      2. 2.5.2 Secure Digital Input Output (SDIO)
        1. 2.5.2.1 SDIO Timing Diagram: Default Speed
        2. 2.5.2.2 SDIO Timing Diagram: High Speed
      3. 2.5.3 Serial Peripheral Interface (SPI)
        1. 2.5.3.1 SPI Timing Diagram
      4. 2.5.4 Universal Asynchronous Receiver-Transmitter (UART)
        1. 2.5.4.1 UART Timing Diagram
      5. 2.5.5 Serial Wire Debug (SWD)
      6. 2.5.6 WLAN Interrupt Request (HOST_IRQ_WL)
      7. 2.5.7 Logger
      8. 2.5.8 Coexistence
  6. 3Layout Considerations – CC33xx Devices
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design – CC330x Single Band Layout
      2. 3.1.2 Reference Design – CC335x Dual Band Layout
      3. 3.1.3 BP-CC3351 Design Layout
      4. 3.1.4 M2-CC3351 Design Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 SDIO
  7. 4Schematic Considerations – CC33xxMOD
    1. 4.1 Schematic Reference Design – CC33xxMOD
    2. 4.2 Power Supply
  8. 5Layout Considerations – CC33xxMOD
    1. 5.1 CC33xxMOD RF Layout Recommendations
  9. 6 CC33xxMOD Regulatory Compliance
    1. 6.1 CC33xxMOD OEM Integration Manual
  10. 7Revision History

2.2 Power Supply

There are two power rails that must be routed to the CC33xx devices:

  • 1.8V: VDD_MAIN_IN, VDDA_IN1, VDDA_IN2, VIO, and VPP_IN
  • 3.3V: PA_LDO_IN

The CC33xx devices have internal LDOs for regulating the digital core, memory, and power amplifier supplies. The output of the LDO can be measured from the DIG_LDO_OUT and PA_LDO_OUT signals.

Note: The output of the PA_LDO_OUT signal is not enabled until firmware is loaded onto the device.

For further information on the operating conditions for the supply pins, see Table 4-9.

Table 2-2 Required Device Power
Pin Signal Direction (I/O) Required Voltage (Typical)
1 PA_LDO_OUT O N/A
31 DIG_LDO_OUT O N/A
17 VIO I 1.8V
32 VDD_MAIN_IN I 1.8V
4 VDDA_IN1 I 1.8V
5 VDDA_IN2 I 1.8V
35 VPP_IN I 1.8V
39 PA_LDO_IN I 3.3V
40