Three types of transients were observed during testing of the ePWMs. These are referred to in subsequent sections as Type 1, Type 2, and Type 3 upsets respectively.

Type 1 upsets occurred local to the PWM, across the pairs of PWM outputs Figure 8-9. This error was self corrected without intervention from the CPU, CPU watchdog or NMI watchdog modules.

Type 2 upsets did not resolve on their own independent of a CPU reset event, caused by either a Watchdog or NMI Watchdog, meant to reset the system in case of a fault. During this testing no fault handling was in place for these events, such that if the watchdog timed out or there was a system level NMI, the system was allowed to reset, and subsequently re-boot to flash. In all cases of a Type 2 upset, after reboot, the system recovered and PWM output resumed as expected. This is not a PWM fault per se, but rather a system upset. The time duration shown in Figure 8-10 is the result of the maximum/default value of the NMI Watchdog resulting boot up time of the device. Figure 8-11 illustrates the effect of change in duty cycle on the complement of PWM 3, that was not corrected until an automatic reset event occurred. It is important to note that due to the critical nature of PWMs complementary outputs, typically driving separate FETs that should not be turned on at the same time, the external FET driver needs to be capable of detecting this illegal condition and not pass the raw PWM to the FET itself. The TPS7H36015-SEP gate driver from TI has interlock protection and can be used in combination with the F28377D-SEP to provide this protection.

Type 3 upsets were unique in that a SEFI occurred, but neither self corrected, nor was corrected by one of the system monitors as in Type 2 upsets. These upsets were rare, however, need to be accounted for in a system design. There was no damage to the device, but the device state was not recovered automatically. Figure 8-12 demostrates the output captured for a Type 3 event, in which both PWM2 outputs go inactive and do not recover by the end of the test run.Figure 8-13 demonstrates another Type 3 event where the ePWM deadband is impacted periodically, but persists for the duration of the SET test.