SPRK066 October   2025 F28377D-SEP

 

  1.   1
  2.   F28377D-SEP Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects (SEE)
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Depth, Range, and LETEFF Calculation
  9. 6Test Setup and Procedures
  10. 7Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
  11. 8Single-Event Transients (SET)
    1. 8.1 GPIO Testing and Results
      1. 8.1.1 GPIO Test Setup
      2. 8.1.2 GPIO SET Analysis
      3. 8.1.3 GPIO SET Summary
    2. 8.2 ePWM Testing and Results
      1. 8.2.1 ePWM Testing Setup
      2. 8.2.2 ePWM SET Analysis
      3. 8.2.3 ePWM SET Summary
    3. 8.3 SRAM Testing and Results
      1. 8.3.1 SRAM Test Setup
      2. 8.3.2 SRAM SET Summary
    4. 8.4 Flash Memory Testing and Results
      1. 8.4.1 Flash Test Setup
      2. 8.4.2 Flash SET Summary
  12. 9Summary
  13.   A Total Ionizing Dose from SEE Experiments
  14.   B References

8.3 SRAM Testing and Results

C2000 controllers, in general have 4 groups of SRAMs:

  • M0/M1 RAMs: Dedicated to the C28x CPU core
  • Pie Vector Table RAM: RAM used to hold the ISR Vectors
  • LSx RAMs: Local Shared RAM, Accessible by both the C28x and CLA
  • GSx RAMs: Global Shared RAM, Accessible by the C28x and DMA
  • Message RAMs: RAM used to communicate between mutliple CPU subsystems.

The F28377D-SEP device also includes additional RAM blocks based on the IP on the device.

  • CAN Message RAM: RAM local to the CAN IP used to buffer message traffic
  • UPP TX/RX Message RAM: RAM local to the UPP IP used to buffer message traffic

Additionally, different RAM types have ECC(Error Correction Code) or Parity to correct or detect errors. ECC is SECDED implementation, Single (Bit) Error Correction, Dual (Bit) Error Detection. This is valid on every 32-bits for RAM and includes the address. Parity implementation is single bit error detect on every 32-bits This is useful in the radiation environment due to both soft and hard errors caused by ion strikes.

The SRAM on the F28377D-SEP also provides access protection logic in HW that can both block and alert to unplanned CPU accesses(either data or program) into specific memory addresses. This can be useful to prevent an ion upset/transient from disrupting code execution.

The below table Table 8-5 provides information on the various SRAM type on the F28377D-SEP device. For additional information on the memory subsystem please refer to the Memory Controller Module section of the device TRM.

Table 8-5 F28377D RAM Types
Memory Type Size Each (KB) ECC-Capable Parity Access Protection
M0,M1 2KB Yes - -
D0, D1 4KB Yes - Yes
LSx 4KB - Yes Yes
GSx 8KB - Yes Yes
MSG RAM 2KB - Yes Yes
PIE Vect RAM 1KB - - -
Note: While the PIE Vector RAM does not have traditional ECC or parity protection, there exists a full backup/duplication of the RAM and a comparison between both values is done on a vector fetch. This is intended to provide coverage for any inconsistencies in the RAM.