SPRADO8A March   2025  – May 2026 AM62L

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Guidelines for Usage of the User's Guide
      1. 1.1.1 Custom Board Schematics Design Guidelines - References Used in the User's Guide
      2. 1.1.2 Processor Family Specific User's Guide
      3. 1.1.3 Schematic Design Guidelines
      4. 1.1.4 Schematic Review Checklist
        1. 1.1.4.1 Common Checklist for Use With All Schematic Design Guidelines and Schematics Review Sections
          1. 1.1.4.1.1 Custom Board Schematic Design Implementation Checklist Sub-Sections Description
      5. 1.1.5 FAQ Reference for User's Guide Usage During Schematic Self-review
    2. 1.2 AM62Lx Processor Family List of Processors
    3. 1.3 Updates to Schematics Design Guidelines and Schematics Review Checklist
  5. 2 Related Collaterals and FAQs
    1. 2.1 Links to Commonly Referenced Collaterals During Custom Board Schematic Design
    2. 2.2 Hardware Design Considerations for Custom Board Design User's Guide
  6. 3 Processor-Specific Information
    1. 3.1 AM62Lx Processor Family Peripherals and IOs Change Summary (With Respect to AM62x Processor Family)
      1. 3.1.1 Silicon Revision
    2. 3.2 Selection of Processor OPN (Orderable Part Number)
    3. 3.3 EVM Schematic Version and Revision Referenced
    4. 3.4 Processor-specific Data Sheet Use Case and Version Referenced for User's Guide Edits
    5. 3.5 Peripheral Instance Naming Convention - Data Sheet and TRM
    6. 3.6 Processor Peripherals and IOs Connection When Not Used (Unused)
    7. 3.7 Ordering and Quality Information for AM62Lx Processor Family
    8. 3.8 Checklist for Selection of Required Processor GPN (Generic Part Number) and OPN (Ordering Part Number)
  7. 4 Processor Power Architecture
    1. 4.1 Generating Processor-Specific and Peripherals (Attached Device) Supply Rails
      1. 4.1.1 AM62Lx Processor Family Power Architecture
        1. 4.1.1.1 Power Management IC (PMIC) Based Power Architecture
          1. 4.1.1.1.1 PMIC Based Power Architecture Checklist for TPS65214x
          2. 4.1.1.1.2 Additional References
        2. 4.1.1.2 Discrete Power Devices (DC/DC, LDO) Based Power Architecture
          1. 4.1.1.2.1 Discrete DC/DCs
          2. 4.1.1.2.2 Discrete LDOs
          3. 4.1.1.2.3 Discrete Power Devices (DC/DC, LDO) Based Power Architecture Checklist
    2. 4.2 Processor Power Rails Supply Control, Sequencing and Supply Overload Protection
      1. 4.2.1 Load Switch (Processor Supply Rail Power Switching)
        1. 4.2.1.1 Load Switch (Processor Supply Rail Power Switching) Checklist
      2. 4.2.2 eFuse IC (Power Switching and Protection)
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (EVM)
      1. 5.1.1 Evaluation Module (Starter Kit) Checklist
    2. 5.2 Processor-Specific EVM Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength or Slew Configuration
        4. 5.2.1.4 Processor-specific Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs Protection - Provision for External ESD Protection Devices
        6. 5.2.1.6 Peripheral Clock Outputs Series Resistor
        7. 5.2.1.7 Peripheral Clock Outputs Pulldown Resistor
        8. 5.2.1.8 Component Selection Checklist
      2. 5.2.2 Additional Information Regarding EVM Design (Schematic, Board) and Reuse
        1. 5.2.2.1 Updated EVM Schematic With Design, Review and CAD Notes Added
        2. 5.2.2.2 EVM Design Files Reuse for Custom Board Design
          1. 5.2.2.2.1 Modular Schematic Sections
          2. 5.2.2.2.2 EVM Design Files Reuse for Custom board Design - Checklist
        3. 5.2.2.3 EVM Schematic Pages Sequencing (Based on Functions, Reuse) and EVM Board Layout
    3. 5.3 Processor-Specific SDK
    4. 5.4 General Design Recommendations (to Know) Before Starting the Custom Board Design
      1. 5.4.1  Processor Documentation
      2. 5.4.2  Processor Pin Attributes (Pinout) Verification
      3. 5.4.3  Device Comparison, IOSET and Voltage Conflict
      4. 5.4.4  RSVD0 Reserved Pin (Signal)
      5. 5.4.5  Note on PADCONFIG Registers
      6. 5.4.6  Processor IO (Signal) Isolation for Fail-Safe Operation
      7. 5.4.7  Pin Connectivity Requirements and Reference to Processor-Specific EVM
      8. 5.4.8  Custom Board High-Speed Interface Design Guidelines
      9. 5.4.9  Recommendations for LVCMOS (GPIO) Output Current Source or Current Sink
      10. 5.4.10 Connection of Slow Ramp Signal (Input) or Capacitor Load (Large Value at the IO Output) to Processor IOs
      11. 5.4.11 Queries Related to Processor and Processor Peripherals Design During Custom Board Design
      12. 5.4.12 General Design Recommendations (to Know) Before Starting the Custom Board Design Checklist
      13. 5.4.13 Attached Devices Recommendations
  9. 6 Processor-Specific Recommendations for Power, Clock, Reset, Boot and Debug
    1. 6.1 Common (Processor Start-Up) Connections
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Core and Peripherals Supplies
          1. 6.1.1.1.1 Power Supply Ramp (Slew Rate) Requirement and Dynamic Voltage Scaling
          2. 6.1.1.1.2 Additional Information
          3. 6.1.1.1.3 Processor Core and Peripheral Core Power Supply Checklist
          4. 6.1.1.1.4 Peripheral Analog Power Supply Checklist
        2. 6.1.1.2 IO Supply for IO Groups
          1. 6.1.1.2.1 Dual-voltage 1.8V/3.3V IO Supply for IO Group
            1. 6.1.1.2.1.1 Dual-voltage IO Supply for IO Group Checklist
          2. 6.1.1.2.2 Fixed-voltage 1.8V IO Supply for (Peripheral) IO Groups
            1. 6.1.1.2.2.1 Fixed-voltage 1.8V IO Supply for (Peripheral) IO Groups Checklist
          3. 6.1.1.2.3 Additional Information
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
          1. 6.1.1.3.1 Supply for VPP Checklist
        4. 6.1.1.4 Supply Connection for Configuring Low-Power Modes
          1. 6.1.1.4.1 External Wakeup Inputs (EXT_WAKEUP0 and EXT_WAKEUP1)
          2. 6.1.1.4.2 RTC Only Low-power Mode
            1. 6.1.1.4.2.1 RTC Only Mode Used
              1. 6.1.1.4.2.1.1 RTC_PORz Delay When RTC Only Mode is Used
              2. 6.1.1.4.2.1.2 EVM Implementation of RTC Only Mode Power Supply Architecture
            2. 6.1.1.4.2.2 Low-Power Mode not Used (RTC Only or RTC + IO + DDR)
              1. 6.1.1.4.2.2.1 32kHz LFOSC0 Clock When RTC Mode is not Used
            3. 6.1.1.4.2.3 RTC Only Low-power Mode Checklist
          3. 6.1.1.4.3 RTC + IO + DDR Self-refresh Low-power Mode
            1. 6.1.1.4.3.1 RTC + IO + DDR Low-Power Mode Used
            2. 6.1.1.4.3.2 Low-Power Mode not Used (RTC Only or RTC + IO + DDR)
            3. 6.1.1.4.3.3 RTC + IO + DDR Self-refresh Low-power Mode Checklist
          4. 6.1.1.4.4 DeepSleep, Standby
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 AM62Lx Processor Family
        2. 6.1.2.2 Additional Information
        3. 6.1.2.3 Capacitors for Supply Rails Checklist
      3. 6.1.3 Processor Clocks (Inputs / Outputs)
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 WKUP_OSC0 (High Frequency) Clock (Internal Oscillator) or LVCMOS Digital Clock (External Oscillator)
          2. 6.1.3.1.2 LFOSC0 (Low Frequency) Clock (Internal Oscillator) or LVCMOS Digital Clock (External Oscillator)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to MAIN Domain)
          4. 6.1.3.1.4 Clock Input Checklist - WKUP_OSC0
          5. 6.1.3.1.5 Clock Input Checklist - LFOSC0
        2. 6.1.3.2 Clock Outputs
          1. 6.1.3.2.1 Clock Output Checklist
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 Reset Status Output
        3. 6.1.4.3 Additional Information
        4. 6.1.4.4 Processor Reset Input Checklist
        5. 6.1.4.5 Processor Reset Status Output Checklist
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Boot Mode Configuration
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Notes on SD Card Boot SDCD Input Connection
        4. 6.1.5.4 Notes on OSPI Boot OSPI Interface Chip Select Connection
        5. 6.1.5.5 Boot Mode Implementation Approaches
        6. 6.1.5.6 Additional Information
        7. 6.1.5.7 Configuration of Boot Modes (for Processor) Checklist
    2. 6.2 Custom Board Debug Using JTAG and EMU
      1. 6.2.1 JTAG Interface and EMU Signals When Used
      2. 6.2.2 JTAG Interface and EMU Signals Connection When Not Used
      3. 6.2.3 Additional Information
      4. 6.2.4 Custom Board Debug Using JTAG and EMU Checklist
  10. 7 Processor Peripherals Power, Interface and Connections
    1. 7.1 Supported Processor Cores
    2. 7.2 Supply Connections for IO Supply for IO Groups
      1. 7.2.1 VDDSHVx Dual-voltage IO Supplies and Fixed-voltage Supplies for IO Groups
      2. 7.2.2 VDDSx Fixed 1.8V Supply
      3. 7.2.3 Supply Connections for IO Supply for IO Groups Checklist
    3. 7.3 Memory Interface (DDRSS (DDR4/LPDDR4), MMCSD (eMMC/SD/SDIO), OSPI/QSPI and GPMC)
      1. 7.3.1 DDR Subsystem (DDRSS)
        1. 7.3.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.3.1.1.1 AM62Lx Processor Family
            1. 7.3.1.1.1.1 Memory Interface Configuration
            2. 7.3.1.1.1.2 Routing Topology and Connection of Memory Terminations
            3. 7.3.1.1.1.3 Resistors for DDRSS Control and Calibration
            4. 7.3.1.1.1.4 Capacitors for the Power Supply Rails
            5. 7.3.1.1.1.5 Data Bit or Byte Swapping
            6. 7.3.1.1.1.6 Unsupported DDRSS Interface Pins
            7. 7.3.1.1.1.7 DDR4 Implementation Checklist
            8. 7.3.1.1.1.8 DDR4 VTT Termination Implementation Schematic Reference
        2. 7.3.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.3.1.2.1 AM62Lx Processor Family
            1. 7.3.1.2.1.1 Memory Interface Configuration
            2. 7.3.1.2.1.2 Routing Topology and Connection of Memory Terminations
            3. 7.3.1.2.1.3 Resistors for DDRSS Control and Calibration
            4. 7.3.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.3.1.2.1.5 Data Bit or Byte Swapping
            6. 7.3.1.2.1.6 LPDDR4 Implementation Checklist
      2. 7.3.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.3.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.3.2.1.1 AM62Lx Processor Family
            1. 7.3.2.1.1.1 IO Power Supply
            2. 7.3.2.1.1.2 eMMC Interface Signals Connection
            3. 7.3.2.1.1.3 eMMC (Attached Device) Reset
            4. 7.3.2.1.1.4 Capacitors for the Power Supply Rails
            5. 7.3.2.1.1.5 MMC0 (eMMC) Checklist
          2. 7.3.2.1.2 Additional Information on eMMC PHY
          3. 7.3.2.1.3 MMC0 – SD (Secure Digital) Card Interface
        2. 7.3.2.2 MMC1/MMC2 – SD (Secure Digital) Card Interface
          1. 7.3.2.2.1 IO Power Supply
          2. 7.3.2.2.2 Signals Connection
            1. 7.3.2.2.2.1 MMC1 Signals Used for SD Card Interface (Recommended)
            2. 7.3.2.2.2.2 MMC2 Signals Used for SD Card Interface
            3. 7.3.2.2.2.3 Additional Information
          3. 7.3.2.2.3 SD Card Power Supply Switch EN Reset Logic
          4. 7.3.2.2.4 External ESD Protection for the SD Card Interface Signals
          5. 7.3.2.2.5 Capacitors for the Dual-voltage IO Supply for IO Groups Supply Rails
          6. 7.3.2.2.6 SD Card Interface (MMC1) Checklist
        3. 7.3.2.3 MMC1/MMC2 SDIO (Embedded) Interface
          1. 7.3.2.3.1 IO Power Supply
          2. 7.3.2.3.2 Signals Connection
          3. 7.3.2.3.3 SDIO (MMC2 Recommended, Embedded) Interface Checklist
        4. 7.3.2.4 Additional Information
      3. 7.3.3 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
        1. 7.3.3.1 OSPI0 Interfaced to Single Device
          1. 7.3.3.1.1 IO Power Supply
          2. 7.3.3.1.2 Signals Connection
          3. 7.3.3.1.3 OSPI/QSPI Device Reset
          4. 7.3.3.1.4 Loopback Clock
        2. 7.3.3.2 Interfaced to x2 Devices
        3. 7.3.3.3 Capacitors for the Power Supply Rails
        4. 7.3.3.4 OSPI0 or QSPI0 Peripheral Interface Implementation Checklist
      4. 7.3.4 General-Purpose Memory Controller (GPMC)
        1. 7.3.4.1 IO Power Supply
        2. 7.3.4.2 GPMC Interface
        3. 7.3.4.3 Signals Connection
          1. 7.3.4.3.1 GPMC NAND
        4. 7.3.4.4 Memory (Attached Device) Reset
        5. 7.3.4.5 Capacitors for the Power Supply Rails
        6. 7.3.4.6 GPMC Interface Checklist
    4. 7.4 External Communication Interface (Ethernet (CPSW3G0), USB2.0, UART and MCAN)
      1. 7.4.1 Ethernet (MAC) Interface
        1. 7.4.1.1 Common Platform Ethernet Switch 3-port Gigabit (CPSW3G0)
          1. 7.4.1.1.1  IO Power Supply
          2. 7.4.1.1.2  MAC (Data, Control and Clock) Interface Signals Connection
          3. 7.4.1.1.3  EPHY Reset
          4. 7.4.1.1.4  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
            1. 7.4.1.1.4.1 Crystal Used as Clock Source for Processor and EPHYs
            2. 7.4.1.1.4.2 External Oscillator Used as Clock Source
            3. 7.4.1.1.4.3 Processor Clock Output (CLKOUT0)
          5. 7.4.1.1.5  Ethernet PHY Pin Strapping
          6. 7.4.1.1.6  External Interrupt (EXTINTn)
            1. 7.4.1.1.6.1 External Interrupt (EXTINTn) Checklist
          7. 7.4.1.1.7  MAC (Media Access Controller) to MAC Interface
          8. 7.4.1.1.8  MDIO (Management Data Input/Output) Interface
          9. 7.4.1.1.9  Ethernet MDI (Medium Dependent Interface) Including Magnetics
          10. 7.4.1.1.10 Capacitors for the Power Supply Rails
          11. 7.4.1.1.11 Ethernet Interface Checklist
      2. 7.4.2 Universal Serial Bus (USB2.0)
        1. 7.4.2.1 USBn (n = 0-1) Interface When Used
          1. 7.4.2.1.1 USB Interface Configured as Host
          2. 7.4.2.1.2 USB Interface Configured as Device
          3. 7.4.2.1.3 USB Interface Configured as Dual-Role-Device
          4. 7.4.2.1.4 USB Type-C
        2. 7.4.2.2 USBn (n = 0-1) Interface Connection When Not Used
        3. 7.4.2.3 Additional Information
        4. 7.4.2.4 USB Interface Checklist
      3. 7.4.3 Universal Asynchronous Receiver/Transmitter (UART)
        1. 7.4.3.1 UART Interface Connection When Not Used
        2. 7.4.3.2 Universal Asynchronous Receiver/Transmitter (UART) Checklist
      4. 7.4.4 Modular Controller Area Network (MCAN) with Full CAN-FD Support
        1. 7.4.4.1 Modular Controller Area Network Checklist
    5. 7.5 On-board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.5.1 Multichannel Serial Peripheral Interface (MCSPI) and Audio Peripheral - Multichannel Audio Serial Port (MCASP)
        1. 7.5.1.1 Connection of MCSPI and MCASP Interface Signals
        2. 7.5.1.2 MCSPI Interface Checklist
        3. 7.5.1.3 MCASP Interface Checklist
      2. 7.5.2 Inter-Integrated Circuit (I2C)
        1. 7.5.2.1 I2C (Open-drain Output Type IO Buffer) Interface Checklist
        2. 7.5.2.2 I2C (Emulated Open-drain Output Type IO) Interface Checklist
    6. 7.6 User Interface (DPI, DSI), GPIO and Hardware Diagnostics
      1. 7.6.1 Display Subsystem (DSS)
        1. 7.6.1.1 Display Parallel Interface (DPI)
          1. 7.6.1.1.1 AM62Lx Processor Family
            1. 7.6.1.1.1.1 IO Power Supply
            2. 7.6.1.1.1.2 Connection
            3. 7.6.1.1.1.3 DPI (Attached Device) Reset
            4. 7.6.1.1.1.4 DPI Signals Connection
            5. 7.6.1.1.1.5 Capacitors for the Power Supply Rail
            6. 7.6.1.1.1.6 DPI (VOUT0) Peripheral Checklist
        2. 7.6.1.2 Display Serial Interface (DSI)
          1. 7.6.1.2.1 AM62Lx Processor Family
            1. 7.6.1.2.1.1 DSITX0 Peripheral Used
              1. 7.6.1.2.1.1.1 DSITX0 Peripheral Checklist
            2. 7.6.1.2.1.2 DSITX0 Peripheral Connection When Not Used
      2. 7.6.2 General Purpose Input/Output (GPIO)
        1. 7.6.2.1 Availability of CLKOUT on Processor GPIO
        2. 7.6.2.2 GPIO Connection and Addition of External Buffer
        3. 7.6.2.3 Additional Information
        4. 7.6.2.4 GPIO Checklist
      3. 7.6.3 On-board Hardware Diagnostics
        1. 7.6.3.1 Internal Temperature Monitoring
          1. 7.6.3.1.1 Internal Temperature Monitoring Checklist
    7. 7.7 Analog to Digital Converter (ADC)
      1. 7.7.1 ADC0 Connections When Used
      2. 7.7.2 ADC0 Connection When Not Used
      3. 7.7.3 ADC0 Checklist
    8. 7.8 EVM Specific Circuit Implementation (Reuse)
    9. 7.9 Performing Board Level Testing During Custom Board Bring-up
      1. 7.9.1 Processor Pin Configuration Using PinMux Tool
      2. 7.9.2 Schematics Configurations
      3. 7.9.3 Connection of Supply Rails to External Pullups
      4. 7.9.4 Peripheral (Subsystem) Clock Outputs
      5. 7.9.5 General Board Bring-up and Debug
        1. 7.9.5.1 Clock Output for Board Bring-Up, Test, or Debug
        2. 7.9.5.2 Additional Information
        3. 7.9.5.3 General Board Bring-up and Debug Checklist
  11. 8 Self-Review of Custom Board Schematic Design
  12. 9 Custom Board Layout Notes (Added Near to the Schematic Sections) and General Guidelines
    1. 9.1 Layout Considerations
  13. 10Custom Board Design Simulation
    1. 10.1 DDR-MARGIN-FW
  14. 11Additional References
    1. 11.1 FAQ Covering AM64x, AM243x, AM62x, AM62Ax, AM62D-Q1, AM62Px, AM62Lx Processor Families
    2. 11.2 FAQs - Processor Product Family Wise and Sitara Processor Families
    3. 11.3 Schematics Review (Self) and Schematic Review Request (Suppliers)
    4. 11.4 Processor Attached Devices Checklist
  15. 12User's Guide Content and Usage Summary
  16. 13References
    1. 13.1  AM62L
    2. 13.2  AM62P, AM62P-Q1
    3. 13.3  AM62A7, AM62A3, AM62A7-Q1, AM62A3-Q1, AM62A1-Q1
    4. 13.4  AM62D-Q1
    5. 13.5  AM625, AM623, AM620-Q1, AM625-Q1, AM625SIP
    6. 13.6  Common for all Processor Families
    7. 13.7  Master List of Available FAQs - Processor Family Wise
    8. 13.8  Master List of Available FAQs - Sitara Processor Families
    9. 13.9  FAQs Including Software Related
    10. 13.10 FAQs for Attached Devices
  17. 14Terminology
  18. 15Revision History
7.4.1.1.3 EPHY Reset

The recommendation is to implement the attached device (EPHY) reset using a 2-input ANDing logic since the ANDing logic provides the flexibility to be able to reset the attached device (EPHY) in all processor reset condition including local reset (in use cases where the attached device becomes non-responsive and needs to be reset without a power cycle). Processor GPIO (used to locally reset the EPHY) is connected as one of the input to the AND gate with provision for pullup (10kΩ or 47kΩ) (to support boot) near to the ANDing logic AND gate input and provision for 0Ω to isolate the GPIO output for testing or debug. The other input to the AND gate is the MAIN domain warm reset status output (RESETSTATz).

When more than one (x2) EPHYs are used, the recommendation is to provide provision to reset the EPHYs individually.

A pullup or pulldown (10kΩ) at the output of the ANDing logic can be used based on the EPHY reset input polarity. The EPHY is required to be held in reset for a specified minimum time after the clock is valid.

In case the processor MAIN domain warm reset status output (RESETSTATz) is directly used (connected) to reset the EPHY (attached device), the recommendation is to match the IO voltage level of RESETSTATz with the attached device. A level translator is recommended to match the IO level. A resistor divider can be used alternatively for level shifting, provided optimum value of the resistor divider is selected. In case the resistor divider value is too high the rise/fall time of the processor IO connected to EPHY reset input can be slow and introduce delay. Use of too low value resistors as divider causes the processor to source too much steady-state current during normal operation.