SBAU412 November   2022 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. Introduction
  4. Prerequisites
  5. Typical Bare-Metal Design Flow
  6. Background
  7. AFE SPI IP Container Pinout
  8. TI AFE SPI IP Container
  9. Create Block Designs With TI AFE SPI IP
  10. Create New Platforms in Vitis
  11. Create New Application Projects in Vitis
  12. 10Build Application Projects
  13. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  14. 12Configure the AXI SPI
  15. 13Create Boot Images to Run on SD Card
  16. 14Set up and Power on Hardware
  17. 15Set up ZCU102 Board Interface for VADJ_FMC
  18. 16Debug Application Projects and Set up Vitis Serial Terminal
  19. 17Execute the Application

Set up and Power on Hardware

To set up and power on the hardware, follow these steps:

  1. Dock the AFE EVM to J5 (HPC0) FMC on the ZCU102 board.
  2. Connect a 1.5-GHz signal through a clock source to RFROM EVM at J14.
  3. Connect J2 (JTAG) and J83 (UART) USB connectors from ZCU102 FPGA board to the computer.
  4. Connect the 12-V Xilinx EVM Adapter for the ZCU102 at J52.
  5. After all the above connections are made, power up the setup. Note that the AFE EVM in this example is completely powered by the ZCU102 FMC interface.