SBAU412 November 2022 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7950
This example uses a soft core Microblaze because the Microblaze can be instantiated in most of the Xilinx FPGA families. The SPI, UART, and GPIO AXI blocks run on relatively lower frequency AXI clocks. As seen in Figure 4-1, the AXI peripherals are controlled by a Microblaze block through smart interconnects.
The interconnection of various submodules within this IP block diagram is similar to typical Microblaze implementations. The HP port of the Microblaze drives AXI peripherals. The clocking of the entire IP is expected from a 100-MHz differential clock source. This example uses a 100-MHz differential clock source because this clock is typically available as ‘user clock’ in most FPGA EVMs. All other clock frequencies are derived internally through a clocking wizard.