SBAU412 November   2022 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 Prerequisites
  5. 3 Typical Bare-Metal Design Flow
  6. 4 Background
  7. 5 AFE SPI IP Container Pinout
  8. 6 TI AFE SPI IP Container
  9. 7 Create Block Designs With TI AFE SPI IP
  10. 8  Create New Platforms in Vitis
  11. 9 Create New Application Projects in Vitis
  12. 10Build Application Projects
  13. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  14. 12Configure the AXI SPI
  15. 13Create Boot Images to Run on SD Card
  16. 14Set up and Power on Hardware
  17. 15Set up ZCU102 Board Interface for VADJ_FMC
  18. 16Debug Application Projects and Set up Vitis Serial Terminal
  19. 17Execute the Application

7 Create Block Designs With TI AFE SPI IP

The IP is expected to be used only within a block design. Users can create a new block design or instantiate the IP within an existing one. To create a new block design with the IP, follow these steps:

  1. Open the IP INTEGRATOR menu and click Create Block Design (see Figure 7-1).
    GUID-20220914-SS0I-ZTLG-JLLW-ZF60R6MNSBXV-low.pngFigure 7-1 Creating Block Design
  2. Enter the desired design name (see Figure 7-2) and keep the other two options as defaults. Click OK.
    GUID-20220914-SS0I-9GJX-1NC1-H1JKRZ1TB9WJ-low.pngFigure 7-2 Naming of Block Design
  3. Click the IP Catalog tab and notice the User Repository header (see Figure 7-3). The header appears only if the inclusion of the IP repository is done correctly, as explained in previous steps.
    GUID-20220914-SS0I-KP7V-VQKV-1WWM0MQSFX5S-low.pngFigure 7-3 User Repository
  4. Double-click AFE79xx SPI Configurator to launch the Add IP window.
  5. Click Add IP to Block Design (see Figure 7-4).
    GUID-20220914-SS0I-SLG5-05GS-DSSWGCG9GXP8-low.pngFigure 7-4 Adding IP to Block Design
  6. The AFE SPI IP shows up in the block design (see Figure 7-5) if the previous steps were followed correctly.
    GUID-20220914-SS0I-6GR8-MGKK-VX0BW8KBKFFL-low.pngFigure 7-5 Final Diagram

The required IOs from the IP must be brought to the top-level file in the FPGA hdl design hierarchy. To do this, first make the required IOs as external. To make the required IOs as external, right-click the individual IOs of interest and select Make External (see Figure 7-6).

GUID-20220914-SS0I-BZZM-XLVV-ZWDXJX6JZFP6-low.pngFigure 7-6 Making IOs External

In the above implementation example, the bare minimum required IOs are brought out as external.

The block design must then be validated for any errors and output products to generate. To validate the block diagram, right-click the block design under the Design Sources header.

Similarly, right-click the View Instantiation Template to use as a reference for wiring this block design on the top level hdl (see Figure 7-7).

GUID-20220914-SS0I-SHJZ-JVS0-LWC46GB4QNRB-low.pngFigure 7-7 TI SPI Configurator Pinout

The IOs from the top level hdl which are connected to this IP must be declared in a Constraints file for them to be mapped to the hardware design, specific FPGA pins, and the correct IO levels.

The above steps complete the hardware design using TI AFE SPI IP.