SBAU412 November   2022 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 Prerequisites
  5. 3 Typical Bare-Metal Design Flow
  6. 4 Background
  7. 5 AFE SPI IP Container Pinout
  8. 6 TI AFE SPI IP Container
  9. 7 Create Block Designs With TI AFE SPI IP
  10. 8  Create New Platforms in Vitis
  11. 9 Create New Application Projects in Vitis
  12. 10Build Application Projects
  13. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  14. 12Configure the AXI SPI
  15. 13Create Boot Images to Run on SD Card
  16. 14Set up and Power on Hardware
  17. 15Set up ZCU102 Board Interface for VADJ_FMC
  18. 16Debug Application Projects and Set up Vitis Serial Terminal
  19. 17Execute the Application

5 AFE SPI IP Container Pinout

GUID-20220919-SS0I-PX92-LBQJ-RC3CZNLTD8KQ-low.png
Table 5-1 Pinout Signals and Connections
SIGNALSDIRECTIONEXTERNAL CONNECTIONS
SPI0_SCLK, SPI0_SDO*, SPI0_SENOutputAFE SPI lines (_SDO* to SDI of AFE)
SPI0_SDIInputAFE SDO
SPI1_SCLK, SPI1_SDO, SPI1_SENOutputLMK SPI lines
RSTZOutputRESETn of AFE

JESD RSTn

JESD TXRST

OutputJESED IP Cores RSTn and TX Rst
RXDInputUART Terminal TX for debug
TXDOutputUART Terminal RX for debug
diff_clock_rtlInput100-Mhz differential clocking
Reset_rtlInputReset (Active High) typically connected to FPGA board reset