SBAU412 November   2022 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 Prerequisites
  5. 3 Typical Bare-Metal Design Flow
  6. 4 Background
  7. 5 AFE SPI IP Container Pinout
  8. 6 TI AFE SPI IP Container
  9. 7 Create Block Designs With TI AFE SPI IP
  10. 8  Create New Platforms in Vitis
  11. 9 Create New Application Projects in Vitis
  12. 10Build Application Projects
  13. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  14. 12Configure the AXI SPI
  15. 13Create Boot Images to Run on SD Card
  16. 14Set up and Power on Hardware
  17. 15Set up ZCU102 Board Interface for VADJ_FMC
  18. 16Debug Application Projects and Set up Vitis Serial Terminal
  19. 17Execute the Application

2 Prerequisites

For effective use of this documentation, ensure to have the following prerequisites:

  • Xilinx Vitis IDE v2020.1.0 (or higher)
  • Xilinx Vivado v2020.1.0 (or higher)
  • Xilinx FPGA board along with TI AFE EVM
  • FPGA bit file download/debug programmer
  • USB-UART cable for debug terminal
  • TI supplied AFE SPI IP
  • TI supplied C-APIs
Table 2-1 Prerequisites
TI AFEAFE79xx
Sample Configuration2T-2R-1FB
Lanes2 RX lanes (1RX, 1FB) and 2 TX lanes at 5 Gbps
AFE EVMAFE79xx EVM
FPGA BoardXilinx ZCU102 EVM