SBAU412 November   2022 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 Prerequisites
  5. 3 Typical Bare-Metal Design Flow
  6. 4 Background
  7. 5 AFE SPI IP Container Pinout
  8. 6 TI AFE SPI IP Container
  9. 7 Create Block Designs With TI AFE SPI IP
  10. 8  Create New Platforms in Vitis
  11. 9 Create New Application Projects in Vitis
  12. 10Build Application Projects
  13. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  14. 12Configure the AXI SPI
  15. 13Create Boot Images to Run on SD Card
  16. 14Set up and Power on Hardware
  17. 15Set up ZCU102 Board Interface for VADJ_FMC
  18. 16Debug Application Projects and Set up Vitis Serial Terminal
  19. 17Execute the Application

1 Introduction

This user guide is a walk-through of complete hardware and software flow to bring up SPI and GPO with TI supplied AFE SPI IP. The hardware in this case refers to the AFE SPI IP supplied by TI which uses a Microblaze processor along with AXI SPI, AXI GPIO, and other required peripherals. Shielding end-customer from the nuances of this setup is one of the core objectives in packaging these in a single custom IP container.

The specific step-wise objectives are as follows:

  • Instantiate TI supplied AFE SPI IP in a Vivado project
  • Map the supplied IP's required signals to FPGA IOs
  • Import hardware design and building a new Vitis application project for software development
  • Compile, link, and download C program to processor along with bit file for FPGA