SBAU412 November   2022 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7950

 

  1.   Abstract
  2.   Trademarks
  3. 1 Introduction
  4. 2 Prerequisites
  5. 3 Typical Bare-Metal Design Flow
  6. 4 Background
  7. 5 AFE SPI IP Container Pinout
  8. 6 TI AFE SPI IP Container
  9. 7 Create Block Designs With TI AFE SPI IP
  10. 8  Create New Platforms in Vitis
  11. 9 Create New Application Projects in Vitis
  12. 10Build Application Projects
  13. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  14. 12Configure the AXI SPI
  15. 13Create Boot Images to Run on SD Card
  16. 14Set up and Power on Hardware
  17. 15Set up ZCU102 Board Interface for VADJ_FMC
  18. 16Debug Application Projects and Set up Vitis Serial Terminal
  19. 17Execute the Application

Abstract

This tutorial guides through the process of using Xilinx Vivado and Vitis development environments along with Texas Instruments supplied custom IP to bring up Serial Peripheral Interface (SPI) and non-timing critical General-Purpose Outputs (GPOs) for Texas Instruments AFE79xx EVM along with the companion LMK series clocking chip, thereby enabling an easier integration of the AFE79xx device into a system design. This guide will demonstrate how to use a Xilinx ZCU102 setup as an example.