ZHCSCA8A March   2014  – April 2019 TPS65286

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      效率
        1.       修订历史记录
  4. 4 Pin Configuration and Functions
    1.     Pin Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Switch
        1. 6.3.1.1 Over Current Condition
        2. 6.3.1.2 Reverse Current and Voltage Protection
        3. 6.3.1.3 nFAULT1/2 Response
        4. 6.3.1.4 Under-Voltage Lockout (UVLO)
        5. 6.3.1.5 Enable and Output Discharge
        6. 6.3.1.6 Power Switch Input and Output Capacitance
        7. 6.3.1.7 Programming the Current-Limit Threshold
      2. 6.3.2 Buck DCDC Converter
        1. 6.3.2.1  Output Voltage
        2. 6.3.2.2  Clock Synchronization
        3. 6.3.2.3  Error Amplifier
        4. 6.3.2.4  Slope Compensation
        5. 6.3.2.5  Enable and Adjusting Under-Voltage Lockout
        6. 6.3.2.6  Soft-Start Time
        7. 6.3.2.7  Internal V7V Regulator
        8. 6.3.2.8  Hard Short Circuit Protection
        9. 6.3.2.9  Bootstrap Voltage (BST) and Low Dropout Operation
        10. 6.3.2.10 Thermal Performance
        11. 6.3.2.11 Loop Compensation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Pulse Skipping Mode Operation
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Step by Step Design Procedure
        2. 7.2.2.2 Related Parts
        3. 7.2.2.3 Inductor Selection
        4. 7.2.2.4 Output Capacitor Selection
        5. 7.2.2.5 Input Capacitor Selection
        6. 7.2.2.6 Soft-Start Capacitor Selection
        7. 7.2.2.7 Minimum Output Voltage
        8. 7.2.2.8 Compensation Component Selection
        9. 7.2.2.9 Auto-Retry Functionality of USB Switches
      3. 7.2.3 Application Performance Plots
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10器件和文档支持
    1. 10.1 器件支持
      1. 10.1.1 第三方产品免责声明
    2. 10.2 接收文档更新通知
    3. 10.3 社区资源
    4. 10.4 商标
    5. 10.5 静电放电警告
    6. 10.6 术语表
  11. 11机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Pin Configuration and Functions

RHD Package
28-Pin VQFN
Top View
TPS65286 po2_slvscg1.gif
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal performance.

Pin Functions

PIN DESCRIPTION
NAME NUMBER
VIN 1, 2, 3 Input power supply for buck. Connect this terminal as close as practical to the (+) terminal of an input ceramic capacitor (suggest 22 µF).
PGND 4, 5, 6 Power ground connection. Connect this terminal as close as practical to the (-) terminal of input capacitor.
V7V 7 Internal low-drop linear regulator (LDO) output. The internal driver and control circuits are powered from this voltage. Decouple this terminal to power ground with a minimum 1-µF ceramic capacitor. The output voltage level of LDO is regulated to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In PCB design, the power ground and analog ground should have one-point common connection at the (-) terminal of V7V bypass capacitor.
MODE/SYNC 8 External synchronization input to internal clock oscillator in forced continuous mode. When an external clock is applied to this terminal, the internal oscillator will force the rising edge of clock signal to be synchronized with the falling edge of the external clock. Connecting this terminal to ground forces a continuous current mode (CCM) operation in buck converter. Connecting this terminal to V7V the buck converter will automatically operate in pulse skipping mode (PSM) at light load condition to save the power.
EN 9 Enable for buck converter. Adjust the input under-voltage lockup with two resistors.
SW_OUT2 10 Power switch 2 output
SW_OUT1 11 Power switch 1 output
SW_EN2 12 Enable power switch 2. There is an internal 1.25-MΩ pull-up resistor connecting this terminal to SW_IN2.
SW_EN1 13 Enable power switch 1. There is an internal 1.25-MΩ pull-up resistor connecting this terminal to SW_IN1.
nFAULT2 14 Active low open drain output, asserted during over-current or reverse-voltage condition of power switch 2.
nFAULT1 15 Active low open drain output, asserted during over-current or reverse-voltage condition of power switch 1.
SW_IN1 16 Power switch input voltage for USB1. Connect to buck output, or other power supply input.
SW_IN2 17 Power switch input voltage for USB2. Connect to buck output, or other power supply input.
BST 18 Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor (recommend 47 nF) from this terminal to LX.
LX 19, 20, 21 Switching node connection to the inductor and bootstrap capacitor for buck converter. This terminal voltage swings from a diode voltage below the ground up to VIN voltage.
SS 22 Soft-start and tracking input for buck converter. An internal 5.5-µA pull-up current source is connected to this terminal. An external soft-start can be programmed by connecting a capacitor between this terminal and ground. Leave the terminal floating to have a default 1ms of soft-start time. This terminal allows the start-up of buck output to track an external voltage using an external resistor divider at this terminal.
FB 23 Feedback sensing terminal for buck output voltage. Connect this terminal to the resistor divider of buck output. The feedback reference voltage is 0.6 V ±1%.
COMP 24 Error amplifier output and Loop compensation terminal for buck. Connect a series resistor and capacitor to compensate the control loop of buck converter with peak current PWM mode.
RLIM 25 BUCK current limit control terminal. An external resistor used to set current limit threshold of buck converter. Recommended 120 kΩ ≤ RLIM ≤ 450kΩ. Connect this terminal to GND, set the current limit to 8 A.
RSET1 26 Power switch current limit control terminal. An external resistor used to set current limit threshold of power switch 1. Recommended 9.1 kΩ ≤ RLIM ≤ 300 kΩ.
RSET2 27 Power switch current limit control terminal. An external resistor used to set current limit threshold of power switch 2. Recommended 9.1 kΩ ≤ RLIM ≤ 300 kΩ.
AGND 28 Analog ground common to buck controller and power switch controller. AGND must be routed separately from high current power grounds to the (-) terminal of bypass capacitor of internal V7V LDO output.
Thermal pad – Exposed pad beneath the IC. Connect to the power ground. Always solder thermal pad to the board, and have as many vias as possible on the PCB to enhance power dissipation. There is no electric signal down bonded to pad inside the IC package.