ZHCSCA8A March   2014  – April 2019 TPS65286

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      效率
        1.       修订历史记录
  4. 4 Pin Configuration and Functions
    1.     Pin Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Switch
        1. 6.3.1.1 Over Current Condition
        2. 6.3.1.2 Reverse Current and Voltage Protection
        3. 6.3.1.3 nFAULT1/2 Response
        4. 6.3.1.4 Under-Voltage Lockout (UVLO)
        5. 6.3.1.5 Enable and Output Discharge
        6. 6.3.1.6 Power Switch Input and Output Capacitance
        7. 6.3.1.7 Programming the Current-Limit Threshold
      2. 6.3.2 Buck DCDC Converter
        1. 6.3.2.1  Output Voltage
        2. 6.3.2.2  Clock Synchronization
        3. 6.3.2.3  Error Amplifier
        4. 6.3.2.4  Slope Compensation
        5. 6.3.2.5  Enable and Adjusting Under-Voltage Lockout
        6. 6.3.2.6  Soft-Start Time
        7. 6.3.2.7  Internal V7V Regulator
        8. 6.3.2.8  Hard Short Circuit Protection
        9. 6.3.2.9  Bootstrap Voltage (BST) and Low Dropout Operation
        10. 6.3.2.10 Thermal Performance
        11. 6.3.2.11 Loop Compensation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Pulse Skipping Mode Operation
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Step by Step Design Procedure
        2. 7.2.2.2 Related Parts
        3. 7.2.2.3 Inductor Selection
        4. 7.2.2.4 Output Capacitor Selection
        5. 7.2.2.5 Input Capacitor Selection
        6. 7.2.2.6 Soft-Start Capacitor Selection
        7. 7.2.2.7 Minimum Output Voltage
        8. 7.2.2.8 Compensation Component Selection
        9. 7.2.2.9 Auto-Retry Functionality of USB Switches
      3. 7.2.3 Application Performance Plots
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10器件和文档支持
    1. 10.1 器件支持
      1. 10.1.1 第三方产品免责声明
    2. 10.2 接收文档更新通知
    3. 10.3 社区资源
    4. 10.4 商标
    5. 10.5 静电放电警告
    6. 10.6 术语表
  11. 11机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.3.2.2 Clock Synchronization

An internal phase locked loop (PLL) has been implemented to allow an external clock with frequency between 200 kHz and 1600 kHz to be synchronized to the internal clock. To implement the synchronization feature, connect a clock signal to the MODE/SYNC terminal with minimum pulse width larger than 80 ns and low/high voltage threshold at 0.4 V/2V. When an external clock is applied to MODE/SYNC terminal, the internal oscillator will force the rising edge of clock signal to be synchronized with the falling edge of the external clock.

TPS65286 clock_synch_slvscg1.gifFigure 25. Clock Synchronization Mode