ZHCSDC1D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 4 | 0x04 | RSV | RSV | RSV | PLCK | RSV | RSV | RSV | PLLE |
| Reset Value | 1 | ||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| PLCK | PLL Lock Flag (Read Only) | ||||||||
| This bit indicates whether the PLL is locked or not. When the PLL is disabled this bit always shows that the PLL is not locked. | |||||||||
| 0: The PLL is locked | |||||||||
| 1: The PLL is not locked | |||||||||
| PLLE | PLL Enable | ||||||||
| This bit enables or disables the internal PLL. When PLL is disabled, the master clock will be switched to the SCK. | |||||||||
| Default value: 1 | |||||||||
| 0: Disable PLL | |||||||||
| 1: Enable PLL | |||||||||