ZHCSDC1D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 42 | 0x2A | RSV | RSV | AUPL1 | AUPL0 | RSV | RSV | AUPR1 | AUPR0 |
| Reset Value | 0 | 1 | 0 | 1 | |||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| AUPL[1:0] | Left DAC Data Path | ||||||||
| These bits control the left channel audio data path connection. | |||||||||
| Default value: 01 | |||||||||
| 00: Zero data (mute) | |||||||||
| 01: Left channel data | |||||||||
| 10: Right channel data | |||||||||
| 11: Reserved (do not set) | |||||||||
| AUPR[1:0] | Right DAC Data Path | ||||||||
| These bits control the right channel audio data path connection. | |||||||||
| Default value: 01 | |||||||||
| 00: Zero data (mute) | |||||||||
| 01: Right channel data | |||||||||
| 10: Left channel data | |||||||||
| 11: Reserved (do not set) | |||||||||