ZHCSDC1D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
| Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
|---|---|---|---|---|---|---|---|---|---|
| 90 | 0x5A | RSV | RSV | RSV | L1OV | R1OV | L2OV | R2OV | SFOV |
| Reset Value | |||||||||
| RSV | Reserved | ||||||||
| Reserved. Do not access. | |||||||||
| L1OV | Left1 Overflow (Read Only) | ||||||||
| This bit indicates whether the left channel of DSP first output port has overflow. This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||
| R1OV | Right1 Overflow (Read Only) | ||||||||
| The bit indicates whether the right channel of DSP first output port has overflow. This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||
| L2OV | Left2 Overflow (Read Only) | ||||||||
| This bit indicates whether the left channel of DSP second output port has overflow. This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||
| R2OV | Right2 Overflow (Read Only) | ||||||||
| The bit indicates whether the right channel of DSP second output port has overflow. This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||
| SFOV | Shifter Overflow (Read Only) | ||||||||
| This bit indicates whether overflow occurred in the DSP shifter (possible sample corruption). This bit is sticky and is cleared when read. | |||||||||
| 0: No overflow | |||||||||
| 1: Overflow occurred | |||||||||