ZHCSEW6G may   2013  – november 2020 DS90UB913A-Q1

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Revision History
  6.   Device Comparison Table
  7. 5Pin Configuration and Functions
    1.     Pin Functions: DS90UB913A-Q1 Serializer
  8. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Timing Diagrams
    10. 6.10 Serializer Switching Characteristics
    11. 6.11 Typical Characteristics
  9. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB913A/914A
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS VDDIO Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB913A/914A Operation with External Oscillator as Reference Clock
      2. 7.4.2 DS90UB913A/914A Operation with Pixel Clock from Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 ID[x] Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  10.   Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  11.   Power Supply Recommendations
  12. 8Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Interconnect Guidelines
    2. 8.2 Layout Example
  13. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
  14.   Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Revision History

Changes from Revision F (January 2020) to Revision G (November 2020)

  • Added register 0x27[3] to register mapGo
  • Clarified PDB voltage level for t3 and t4 in Power-Up Sequencing from 90% VPDB to PDB VIH Go
  • Changed Power-Up Sequencing alternative programming steps (t3*) to add NCLK resetGo
  • Clarified Power-Up Sequencing alternative programming steps (t3*) to remove delay between I2C commandsGo

Changes from Revision E (September 2018) to Revision F (January 2020)

  • Clarified GPO2 description by removing statement about leaving pin open if unused Go
  • Added register 0x27[5] to register map Go
  • Fixed missing register 0x29 typo Go
  • Added maximum power up timing constraint between VDD_n and PDB Go
  • Added recommended software programming steps if VDD_n to PDB maximum power up timing constraint can not be met Go

Changes from Revision D (October 2016) to Revision E (September 2018)

  • Added recommendation to ensure GPO2 is low when PDB goes high Go
  • Added Power Over Coax supply noise to the recommended operating conditions tableGo
  • Clarified PCLK clock frequency range and added external clock input frequency rangeGo
  • Added strap pin input current specification for MODE and IDX pins Go
  • Updated TJIT1 PCLK input jitter in the external oscillator mode Go
  • Added clarification on MODE pin description in PCLK from imager mode Go
  • Updated pullup and pulldown resistor to R1 and R2 in MODE pin configuration diagram Go
  • Updated the MODE setting values to ratioGo
  • Updated pullup and pulldown resistor for IDX to R3 and R4 in the diagramGo
  • Updated IDX setting values to ratio Go
  • Updated register "TYPE" column per legend Go
  • Added type and default value to the reserved register bits that were missing this information Go
  • Added that register 0x00[7:1] does not auto update IDX strapped address Go
  • Added description for 0x05 bits 1 and 0 (TX_MODE_12b and TX_MODE_10b) Go
  • Clarified description on PDB pin usage during power up Go
  • Added paragraph to explain setting registers if GPO2 state is not determined when PDB goes high Go
  • Added GPO2 to suggested power-up sequencing diagram Go
  • Added timing constraint for PDB to GPO2 delay Go
  • Revised coax connection diagram to include pulldown resistor for GPO2 Go
  • Revised STP connection diagram to include pulldown resistor for GPO2 Go

Changes from Revision C (April 2016) to Revision D (August 2016)

  • Added back channel line rate = 5.5 MHz as test condition; also added footnote for clarification between MHz and Mbps distinction.Go
  • Removed 'ns' unit from specifications referencing period in units of T.Go
  • Updated test condition specs for jitter bandwidth regarding tJIT0, tJIT1, and tJIT2.Go
  • Added input external oscillator frequency range for pin/freq. Go
  • Added parameter for typical external oscillator frequency stability.Go
  • Added test conditions to tJIND, tJINR, and tJINT.Go
  • Added DOUT± as measured output pins for jitter parameters.Go
  • Added note (6) for "Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input". Go
  • Added jitter tolerance curve for typical system IJT configuration with DS90UB913A linked to DS90UB914A. Go
  • Added device functional mode table for external oscillator operation with example XCLKIN = 48MHz. Go

Changes from Revision B (December 2014) to Revision C (March 2016)

  • 已将文档拆分为两个独立文档（器件 DS90UB913A-Q1 和 DS90UB914A-Q1）。Go
  • 修改了汽车类特性Go
  • Updated pin description for DIN to include active/inactive outputs corresponding to MODE setting.Go
  • Added pin description to GPO pins to leave open if unused. Go
  • Changed Air Discharge ESD Rating (IEC61000-4-2: RD = 330 Ω, CS = 150 pF) to minimum ±25000 V. Go
  • Added RTV text to Thermal Information tableGo
  • Added GPO[3:0] typical pin capacitances. Go
  • Changed Differential Output Voltage minimum specification. Go
  • Changed Single-Ended Output Voltage minimum specification.Go
  • Added Back Channel Differential Input Voltage minimum specification.Go
  • Added Back Channel Single-Ended Input Voltage minimum specification.Go
  • Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=100 MHz, 10-bit mode to typical value of 65 mA; value is currently 54 mA.Go
  • Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=75 MHz, 12-bit high freq mode to typical value of 64 mA; value is currently 54 mA.Go
  • Updated IDDT for VDD_n=1.89V, VDDIO=3.6V, RL=100Ω, Random Pattern with f=50 MHz, 12-bit low freq mode to typical value of 63 mA; value is currently 54 mA. Go
  • Updated frequency ranges for MODE settings and also revised with correct maximum clock periods. Added footnote and nominal clock period to be in terms of 'T'. Go
  • Deleted Revised jitter freq. test conditions to be > f/20 and also updated typical values for tjit0and tjit2.Go
  • Updated VOL Output Low Level row with revised IOL currents and max VOL voltages, dependent upon VDD IO voltage. Go
  • Updated Figure 2 title to state ‘“Worst-Case” Test Pattern for Power Consumption’. Go
  • Added footnote that states the following: “UI – Unit Interval is equivalent to one serialized data bit width. The UI scales with PCLK frequency.” Add below calculations to footnote. 12-bit LF mode 1 UI = 1 / ( PCLK_Freq. x 28 ) 12-bit HF mode 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 ) 10-bit mode 1 UI = 1 / ( PCLK_Freq. /2 x 28 ) Go
  • Updated frequency requirements for 10-bit and 12-bit HF modes. 10-bit mode – 50 MHz to 100 MHz; 12-bit HF mode – 37.5 MHz to 75 MHz; 12-bit LF mode (no change) – 25 MHz to 50 MHz. Go
  • Updated register 0x01[1] default value to be “0”.Go
  • Changed GPO0 Enable for 0x0D[4] to GPO1 Enable.Go
  • Added Inject Forward Channel Error Register 0x2D.Go
  • Updated power up sequencing information and timing diagram. Go
  • Added description specifying that the voltage applied on VDDIO (1.8 V, 3.3 V) or VDD_n (1.8 V) should be at the input pin – any board level DC drop should be compensated. Go
  • Added 913A EVM layout example image. Go

Changes from Revision A (June 2013) to Revision B (December 2014)

  • 添加了数据表流程和布局，以便符合新的 TI 标准。添加了以下部分：器件比较表；处理额定值；应用和实施；电源建议；布局；器件和文档支持；机械、封装和可订购信息Go
  • Added additional thermal characteristics.Go
  • Changed typo in Vout test condition from RL=500Ω to RL=50Ω. Go
  • Changed Figure 6-6 to use VODp-p and to clarify difference between STP and CoaxGo
  • Added Internal Oscillator section to Device Functional ModesGo
  • Added reference to Power over Coax Application reportGo
  • Added power up sequencing information and timing diagram.Go