ZHCSEW6G may 2013 – november 2020 DS90UB913A-Q1
PRODUCTION DATA
The chipset can be programmed into BIST mode using either pins or registers on the DES only. By default, BIST configuration is controlled through pins. BIST can be configured via registers using BIST Control register (0x24). Pin-based configuration is defined as follows:
| DESERIALIZER GPIO[0:1] | OSCILLATOR SOURCE | BIST FREQUENCY |
|---|---|---|
| 00 | External PCLK | PCLK or External Oscillator |
| 01 | Internal | ~50 MHz |
| 10 | Internal | ~25 MHz |
| DS90UB914A-Q1 Reg 0x24 [2:1] | 10–BIT MODE | 12–BIT HIGH-FREQUENCY MODE | 12–BIT LOW-FREQUENCY MODE |
|---|---|---|---|
| 00 | PCLK | PCLK | PCLK |
| 01 | 100 MHz | 75 MHz | 50 MHz |
| 10 | 50 MHz | 37.5 MHz | 25 MHz |
| 11 | Reserved | Reserved | Reserved |
BIST mode provides various options for the PCLK source. Either external pins (GPIO0 and GPIO1) or registers can be used to program the BIST to use external PCLK or various OSC frequencies. Refer to Table 7-4 for pin settings. The BIST status can be monitored real-time on the PASS pin. For every frame with error(s), the PASS pin toggles low for one-half PCLK period. If two consecutive frames have errors, PASS will toggle twice to allow counting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST run only for one PCLK cycle. The status can also be read through I2C for the number of frames in errors. BIST status register retains results until it is reset by a new BIST session or a device reset. To evaluate BIST in external oscillator mode, both the external oscillator and PCLK need to be present. For all practical purposes, the BIST status can be monitored from the BIST Error Count register 0x25 on the DS90UB914A Deserializer.