ZHCSEW6G may   2013  – november 2020 DS90UB913A-Q1

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Revision History
  6.   Device Comparison Table
  7. 5Pin Configuration and Functions
    1.     Pin Functions: DS90UB913A-Q1 Serializer
  8. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Timing Diagrams
    10. 6.10 Serializer Switching Characteristics
    11. 6.11 Typical Characteristics
  9. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB913A/914A
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS VDDIO Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB913A/914A Operation with External Oscillator as Reference Clock
      2. 7.4.2 DS90UB913A/914A Operation with Pixel Clock from Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 ID[x] Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  10.   Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  11.   Power Supply Recommendations
  12. 8Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Interconnect Guidelines
    2. 8.2 Layout Example
  13. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
  14.   Mechanical, Packaging, and Orderable Information

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8.1.2 Power-Up Requirements and PDB Pin

Clarified PDB voltage level for t3 and t4 in Power-Up Sequencing from 90% VPDB to PDB VIH

Clarified PDB voltage level for t3 and t4 in Power-Up Sequencing from 90% VPDB to PDB VIH

Transition of the PDB pin from LOW to HIGH must occur after the VVDDIO and VVDD_n supplies have reached their required operating voltage levels. Direct control of the PDB timing by processor GPIO is recommended if possible. When direct control of PDB is not available, the PDB pin can be tied to the power supply rail with an RC filter network to help ensure proper power up timing. GPO2 should be low when PDB goes high. Timing constraints are noted in Figure 8-1 and Table 8-1. Please refer to Section 7.3.8 for device operation when powered down.

If GPO2 state is not determined when PDB goes high, DS90UB913A registers must be programmed to configure the transmission mode. Mode Select register 0x05[5] must be set to 1 and register 0x05 bit 1 and 0 are to be selected based on desired 12-bit or 10-bit transmit data format.

Common applications will tie the VDDIO and VDD_n supplies to the same power source of 1.8 V typically. This is an acceptable method for ramping the VDDIO and VDD_n supplies. The main constraint here is that the VDD_n supply does not lead in ramping before the VDDIO system supply. This is noted in Figure 8-1 with the requirement of t1≥ 0. VDDIO should reach the expected operating voltage earlier than VDD_n or at the same time.

GUID-C92A0CA4-F7B7-46B4-BB70-650B531440F1-low.gifFigure 8-1 Suggested Power-Up Sequencing
Table 8-1 Power-Up Sequencing Constraints for DS90UB913A-Q1
SYMBOLDESCRIPTIONTEST CONDITIONSMINTYPMAXUnits
t0V(VDDIO) rise time10% to 90% of nominal voltage on rising edge. Monotonic signal ramp is required0.055ms
t1V(VDDIO) to V(VDD_n) delay10% of rising edge (V(VDDIO)) to 10% of rising edge (V(VDD_n))0ms
t2V(VDD_n) rise time10% to 90% of nominal voltage on rising edge. Monotonic signal ramp is required. VPDB < 10% of V(VDDIO)0.055ms
t3*V(VDD_n) to PDB VIH delay90% rising edge (V(VDD_n)) to PDB VIH016ms
t4PDB to GPO2 delayPDB VIH to 10% of rising edge (GPO2)1.3ms

* If timing constraint t3 cannot be assured, the following programming steps should be issued to the DS90UB913A-Q1 via local I2C control (not via remote back channel). These programming steps should be completed > 10ms after the power sequence is complete (VPDB > PDB VIH) with no delay between write commands. This step will cause a brief restart of the forward channel output:

  • Write Register 0x27 = 0x28
  • Write Register 0x27 = 0x20
  • Write Register 0x27 = 0x00