ZHCSEW6G may   2013  – november 2020 DS90UB913A-Q1

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Revision History
  6.   Device Comparison Table
  7. 5Pin Configuration and Functions
    1.     Pin Functions: DS90UB913A-Q1 Serializer
  8. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Recommended Serializer Timing For PCLK
    7. 6.7  AC Timing Specifications (SCL, SDA) - I2C-Compatible
    8. 6.8  Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
    9. 6.9  Timing Diagrams
    10. 6.10 Serializer Switching Characteristics
    11. 6.11 Typical Characteristics
  9. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Frame Format
      2. 7.3.2 Line Rate Calculations for the DS90UB913A/914A
      3. 7.3.3 Error Detection
      4. 7.3.4 Synchronizing Multiple Cameras
      5. 7.3.5 General Purpose I/O (GPIO) Descriptions
      6. 7.3.6 LVCMOS VDDIO Option
      7. 7.3.7 Pixel Clock Edge Select (TRFB / RRFB)
      8. 7.3.8 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DS90UB913A/914A Operation with External Oscillator as Reference Clock
      2. 7.4.2 DS90UB913A/914A Operation with Pixel Clock from Imager as Reference Clock
      3. 7.4.3 MODE Pin on Serializer
      4. 7.4.4 Internal Oscillator
      5. 7.4.5 Built In Self Test
      6. 7.4.6 BIST Configuration and Status
      7. 7.4.7 Sample BIST Sequence
    5. 7.5 Programming
      1. 7.5.1 Programmable Controller
      2. 7.5.2 Description of Bidirectional Control Bus and I2C Modes
      3. 7.5.3 I2C Pass-Through
      4. 7.5.4 Slave Clock Stretching
      5. 7.5.5 ID[x] Address Decoder on the Serializer
      6. 7.5.6 Multiple Device Addressing
    6. 7.6 Register Maps
  10.   Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
      2. 8.1.2 Power-Up Requirements and PDB Pin
      3. 8.1.3 AC Coupling
      4. 8.1.4 Transmission Media
    2. 8.2 Typical Applications
      1. 8.2.1 Coax Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 STP Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  11.   Power Supply Recommendations
  12. 8Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Interconnect Guidelines
    2. 8.2 Layout Example
  13. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
  14.   Mechanical, Packaging, and Orderable Information

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7.6 Register Maps

In the register definitions under the TYPE and DEFAULT heading, the following definitions apply:

  • R = Read only access
  • R/W = Read / Write access
  • R/RC = Read only access, Read to Clear
  • (R/W)/SC = Read / Write access, Self-Clearing bit
  • (R/W)/S = Read / Write access, Set based on strap pin configuration at startup
  • LL = Latched Low and held until read
  • LH = Latched High and held until read
  • S = Set based on strap pin configuration at startup
Table 7-7 DS90UB913A-Q1 Control Registers(6)
Addr (Hex) Name Bits Field TYPE Default Description
0x00 I2C Device ID 7:1 DEVICE ID R/W 0xB0'h
(1011_0000'b)		 7-bit address of Serializer (0x58'h default).
This field does not auto update IDX strapped address.
0 Serializer ID SEL 0: Device ID is from ID[x].
1: Register I2C Device ID overrides ID[x].
0x01 Power and Reset 7 RSVD R/W 0 Reserved.
6 RDS R/W 0 Digital Output Drive Strength.
1: High Drive Strength.
0: Low Drive Strength.
5 VDDIO Control R/W 1 Auto Voltage Control.
1: Enable.
0: Disable.
4 VDDIO MODE R/W 1 VDDIO Voltage set.
1: VDDIO = 3.3 V.
0: VDDIO = 1.8 V.
3 ANAPWDN R/W 0 This register can be set only through local I2C access.
1: Analog power down. Powers down the analog block in the Serializer.
0: No effect.
2 RSVD R/W 0 Reserved.
1 DIGITAL
RESET1		 R/W 0 1: Resets the digital block except for register values. Does not affect device I2C Bus or Device ID. This bit is self-clearing.
0: Normal Operation.
0 DIGITAL
RESET0		 R/W 0 1: Digital Reset, resets the entire digital block including all register values. This bit is self-clearing.
0: Normal Operation.
0x02 Reserved
0x03 General Configuration 7 RX CRC Checker Enable R/W 1 Back-channel CRC checker enable
1: Enable
0: Disable
6 TX Parity Generator Enable R/W 1 Forward channel parity generator enable.
1: Enable
0: Disable
5 CRC Error Reset R/W 0 Clear CRC error counters
This bit is NOT self-clearing.
1: Clear counters
0: Normal operation
4 I2C Remote Write Auto Acknowledge R/W 0 Automatically acknowledge I2C remote write
The mode works when the system is LOCKed.
1: Enable: When enabled, I2C writes to the deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately acknowledged without waiting for the deserializer to acknowledge the write. The accesses are then remapped to address specified in 0x06.
0: Disable
3 I2C Pass-Through All R/W 0 1: Enable Forward Control Channel pass-through of all I2C accesses to I2C IDs that do not match the serializer I2C ID. The I2C accesses are then remapped to address specified in register 0x06.
0: Enable Forward Control Channel pass-through only of I2C accesses to I2C IDs matching either the remote deserializer ID or the remote I2C IDs.
2 I2C Pass-Through R/W 1 I2C Pass-through mode
1: Pass-through enabled. DES alias 0x07 and slave alias 0x09
0: Pass-through disabled
1 OV_CLK2PLL R/W 0 1:Enabled : When enabled this register overrides the clock to PLL mode (External Oscillator mode or Direct PCLK mode) defined through MODE pin and allows selection through register 0x35 in the serializer.
0: Disabled : When disabled, Clock to PLL mode (External Oscillator mode or Direct PCLK mode) is defined through MODE pin on the Serializer.
0 TRFB R/W 1 Pixel clock edge select
1: Parallel interface data is strobed on the rising clock edge
0: Parallel interface data is strobed on the falling clock edge
0x04 Reserved.
0x05 Mode Select 7 RSVD R/W 0 Reserved.
6 RSVD R/W 0 Reserved.
5 MODE_
OVERRIDE		 R/W 0 Allows overriding mode select bits coming from back-channel.
1: Overrides MODE select bits.
0: Does not override MODE select bits.
4 MODE_UP_
TO_DATE		 R 0 1: Status of mode select from Deserializer is up-to-date.
0: Status is NOT up-to-date.
3 Pin_MODE_
12–bit High Frequency		 R 0 1: 12-bit high frequency mode is selected.
0: 12-bit high frequency mode is not selected.
2 Pin_MODE_
10–bit mode		 R 0 1: 10-bit mode is selected.
0: 10-bit mode is not selected.
1 TX_MODE_12b R/W 0 Selects 12 bit data-bus. This bit changes the Tx mode settings if MODE_OVERRIDE is SET 0x05[5] = 1.
1: Enables 12 bit HF mode
0: Disables 12 bit HF mode
Note: This bit changes mode settings on TX. When TX_MODE_12b is set TX_MODE_10b must be cleared; 0x05[1:0] = 10.
0 TX_MODE_10b R/W 0 Selects 10 bit data-bus. This bit changes the Tx mode settings if MODE_OVERRIDE is SET 0x05[5] = 1.
1: Enables 10b mode
0: Disables 10b mode
Note: This bit changes mode settings on TX. When TX_MODE_10b is set TX_MODE_12b must be cleared; 0x05[1:0] = 01.
0x06 DES ID 7:1 Deserializer Device ID R/W 0x00'h 7-bit Deserializer Device ID Configures the I2C Slave ID of the remote Deserializer. A value of 0 in this field disables I2C access to the remote Deserializer. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the Bidirectional Control Channel.
0 Freeze Device ID R/W 0 1: Prevents auto-loading of the Deserializer Device ID by the bidirectional control channel. The ID will be frozen at the value written.
0: Update.
0x07 DES Alias 7:1 Deserializer ALIAS ID R/W 0x00 7-bit remote deserializer device alias ID Configures the decoder for detecting transactions designated for an I2C deserializer device. The transaction is remapped to the address specified in the DES ID register.
A value of 0 in this field disables access to the remote deserializer.
0 RSVD R/W 0 Reserved
0x08 SlaveID 7:1 SLAVE ID R/W 0x00'h 7-bit Remote Slave Device ID Configures the physical I2C address of the remote I2C Slave device attached to the remote Deserializer. If an I2C transaction is addressed to the Slave Alias ID, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer and then to remote slave. A value of 0 in this field disables access to the remote I2C slave.
0 RSVD R/W 0 Reserved.
0x09 Slave Alias 7:1 SLAVE ALIAS ID R/W 0x00'h 7-bit Remote Slave Device Alias ID Configures the decoder for detecting transactions designated for an I2C Slave device attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID register. A value of 0 in this field disables access to the remote I2C Slave.
0 RSVD R/W 0 Reserved.
0x0A CRC Errors 7:0 CRC Error Byte 0 R 0x00'h Number of back-channel CRC errors during normal operation. Least Significant byte.
0x0B CRC Errors 7:0 CRC Error Byte 1 R 0x00'h Number of back-channel CRC errors during normal operation. Most Significant byte.
0x0C General Status 7:5 Rev-ID R 0x0'h Revision ID.
0x0: Production Revision ID.
4 RX Lock Detect R 0 1: RX LOCKED.
0: RX not LOCKED.
3 BIST CRC
Error Status		 R 0 1: CRC errors in BIST mode.
0: No CRC errors in BIST mode.
2 PCLK Detect R 0 1: Valid PCLK detected.
0: Valid PCLK not detected.
1 DES Error R 0 1: CRC error is detected during communication with Deserializer.
This bit is cleared upon loss of link or assertion of CRC ERROR RESET in register 0x03[5].
0: No effect.
0 LINK Detect R 0 1: Cable link detected.
0: Cable link not detected.
This includes any of the following faults:
— Cable Open.
— '+' and '-' shorted.
— Short to GND.
— Short to battery.
0x0D GPO[0]
and GPO[1]
Configuration		 7 GPO1 Output Value R/W 0 Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled. The local GPIO direction is Output, and remote GPIO control is disabled.
6 GPO1 Remote Enable R/W 1 Remote GPIO Control.
1: Enable GPIO control from remote Deserializer. The GPIO pin needs to be an output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
5 RSVD R/W 0 Reserved.
4 GPO1 Enable R/W 1 1: GPIO enable.
0: Tri-state.
3 GPO0 Output Value R/W 0 Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled. The local GPIO direction is Output, and remote GPIO control is disabled.
2 GPO0 Remote Enable R/W 1 Remote GPIO Control.
1: Enable GPIO control from remote Deserializer. The GPIO pin needs to be an output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1 RSVD R/W 0 Reserved.
0 GPO0 Enable R/W 1 1: GPIO enable.
0: Tri-state.
0x0E GPO[2]
and GPO[3]
Configuration		 7 GPO3 Output Value R/W 0 Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled. The local GPIO direction is Output, and remote GPIO control is disabled.
6 GPO3 Remote Enable R/W 0 Remote GPIO Control.
1: Enable GPIO control from remote Deserializer. The GPIO pin needs to be an output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
5 GPO3 Direction R/W 1 1: Input.
0: Output.
4 GPO3 Enable R/W 1 1: GPIO enable.
0: Tri-state.
3 GPO2 Output Value R/W 0 Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled. The local GPIO direction is Output, and remote GPIO control is disabled.
2 GPO2 Remote Enable R/W 1 Remote GPIO Control.
1: Enable GPIO control from remote Deserializer. The GPIO pin needs to be an output, and the value is received from the remote Deserializer.
0: Disable GPIO control from remote Deserializer.
1 RSVD R/W 0 Reserved.
0 GPO2 Enable R/W 1 1: GPIO enable.
0: Tri-state.
0x0F I2C Master Config 7:5 RSVD R 0x0'h Reserved.
4:3 SDA Output Delay R/W 00 SDA Output Delay This field configures output delay on the SDA output. Setting this value will increase output delay in units of 50ns. Nominal output delay values for SCL to SDA are:
00: ~350 ns
01: ~400 ns
10: ~450 ns
11: ~500 ns
2 Local Write Disable R/W 0 Disable Remote Writes to Local Registers Setting this bit to a 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Serializer registers from an I2C master attached to the Deserializer. Setting this bit does not affect remote access to I2C slaves at the Serializer.
1 I2C Bus Timer Speed up R/W 0 Speed up I2C Bus Watchdog Timer.
1: Watchdog Timer expires after approximately 50 microseconds.
0: Watchdog Timer expires after approximately 1 second.
0 I2C Bus Timer Disable R/W 0 1. Disable I2C Bus Watchdog Timer When the I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1 second, the I2C bus will assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL.
0: No effect.
0x10 I2C Control 7 RSVD R/W 0 Reserved.
6:4 SDA Hold Time R/W 0x1'h Internal SDA Hold Time. This field configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 50 ns.
3:0 I2C Filter Depth R/W 0x7'h I2C Glitch Filter Depth. This field configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 10 ns.
0x11 SCL High Time 7:0 SCL High Time R/W 0x82'h I2C Master SCL High Time This field configures the high pulse width of the SCL output when the Serializer is the Master on the local I2C bus. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum (4 µs + 1 µs of rise time for cases where rise time is very fast) SCL high time with the internal oscillator clock running at 26 MHz rather than the nominal 20 MHz.
0x12 SCL LOW Time 7:0 SCL Low Time R/W 0x82'h I2C SCL Low Time This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 50 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum (4.7 µs + 0.3 µs of fall time for cases where fall time is very fast) SCL low time with the internal oscillator clock running at 26MHz rather than the nominal 20MHz.
0x13 General Purpose Control 7:0 GPCR[7:0] R/W 0x00'h 1: High.
0: Low.
0x14 BIST Control 7:5 RSVD R 0x0'h Reserved.
4:3 RSVD R/W 0x0'h Reserved.
2:1 Clock Source R/W 0x0'h Allows choosing different OSC clock frequencies for forward channel frame.
OSC Clock Frequency in Functional Mode when OSC mode is selected or when the selected clock source is not present, for example, missing PCLK/ External Oscillator. See Table 7-3 for oscillator clock frequencies when PCLK/ External Clock is missing.
0 RSVD R/W 0 Reserved.
0x15 -
0x1D		 Reserved.
0x1E BCC Watchdog Control 7:1 BCC Watchdog Timer R/W 0x7F'h
(111_1111'b)		 The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 ms. This field should not be set to 0.
0 BCC Watchdog Timer Disable R/W 0 1: Disables BCC Watchdog Timer operation.
0: Enables BCC Watchdog Timer operation.
0x1F -
0x26		 Reserved
0x27 Analog Power Down Control 7:6 Reserved R 0 Reserved
5 Power Down PLL RW 0 1: Power down forward channel PLL
0: Normal operation
4 Reserved RW 0 Reserved
3 Power Down NCLK RW 0 1: Power down NCLK
0: Normal operation
2:0 Reserved RW 0 Reserved
0x28 Reserved
0x29 OSC Divider 7:6 RSVD R/W 0x0 Reserved
5 OSC Divider R/W 0 Selects the OSC frequency to drive out on GPO2 in external oscillator mode.
0: Divide by 2 (default)
1: Divide by 4
4:0 RSVD R/W 0x06 Reserved
0x2A CRC Errors 7:0 BIST Mode CRC Errors Count R 0x00'h Number of CRC Errors in the back channel when in BIST mode.
0x2B -
0x2C		 Reserved.
0x2D Inject Forward Channel Error 7 Force Forward Channel Error R/W 0 1: Forces 1 (one) error over forward channel frame in normal operating mode. Self clearing bit.
0: No error.
6:0 Force BIST Error R/W 0x00'h N: Forces N number of errors in BIST mode. This register MUST be set BEFORE BIST mode is enabled.
BIST Error Count Register on the deserializer (i.e. 0x25 on 914A device) should be read AFTER BIST mode is disabled for the correct number of errors incurred while in BIST mode.
0: No error.
0x2E -
0x34		 Reserved.
0x35 PLL Clock Overwrite 7:4 RSVD R/W 0x0'h Reserved.
3 PIN_LOCK to External Oscillator R 0 Status of mode select pin.
1: Indicates External Oscillator mode is selected by mode-resistor.
0: External Oscillator mode is not selected by mode-resistor.
2 RSVD R 0 Reserved.
1 LOCK to External Oscillator R/W 0 Affects only when 0x03[1]=1 (OV_CLK2PLL) and 0x35[0]=0.
1: Routes GPO3 directly to PLL.
0: Allows PLL to lock to PCLK.
0 LOCK2OSC R/W 1 Affects only when 0x03[1]=1 (OV_CLK2PLL).
1: Allows internal OSC clock to feed into PLL.
0: Allows PLL to lock to either PCLK or external clock from GPO3.