ZHCSIS3B 数据表 | 德州仪器 TI.com.cn

ZHCSIS3B September 2018 – December 2022 DP83869HM

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RGZ|48
- MPQF123F

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8.6 Timing Requirements

PARAMETER		MIN	NOM	MAX	UNIT
POWER-UP TIMING (2, 3 supply mode)
T1	Last Supply power up To Reset Release: External or via R-C network	200			ms
T2	Powerup to SMI ready: Post power-up stabilization time prior to MDC preamble for register access		200		ms
T3	Powerup to Strap latchin: Hardware configuration pins transition to output drivers		200		ms
RESET TIMING
T1	Reset to SMI ready: Post reset stabilization time prior to MDC preamble for register access	30			us
T3	RESET PULSE Width: Miminum Reset pulse width to be able to reset	720			ns
T4	Reset to FLP		1750		ms
T4	Reset to 100M signaling (strapped mode)		194		us
T4	Reset to 1G signaling (strapped mode)		194		us
T4	Reset to Fiber 100M signaling		248		us
T4	Reset to Fiber 1G ANEG signaling		235		us
T4	Reset to Fiber 1G Forced signaling		235		us
T4	Reset to MAC clock (Cu mode)		195		us
T4	Reset to MAC clock (Fi mode)		248		us
T4	Reset to MAC clock (S2R)		248		us
T4	Reset to MAC clock (R2S)		248		us
COPPER LINK TIMING
T1	Loss of Idles to Link LED low in Fast link down mode (100M)		4.3	10	us
T1	Loss of Idles to Link LED low in Fast link down mode (1000M)		7	10	us
MII TIMING (100M)
T1	TX_CLK High / Low Time	16	20	24	ns
T2	TX_D[3:0], TX_ER, TX_EN Setup to TX_CLK	10			ns
T3	TX_D[3:0], TX_ER, TX_EN Hold from TX_CLK	0			ns
T1	RX_CLK High / Low Time	16	20	24	ns
T2	RX_D[3:0], RX_ER, RX_DV Delay from RX_CLK rising	10		30	ns
RGMII OUTPUT TIMING (1G)
T_skewT	Data to Clock Output Skew (Non-Delay Mode)	-600		600	ps
T_skewT(Delay)	Data to Clock Output Setup (Delay Mode)	1.4		2.6	ns
T_setupT	Data to Clock Output Setup ( Delay Mode)	1.2			ns
T_holdT	Data to Clock Output Hold ( Delay Mode)	1.2			ns
T_cyc	Clock Cycle Duration	7.2	8	8.8	ns
	Duty Cycle	45	50	55	%
	Rise / Fall Time ( 20% to 80%)			0.75	ns
RGMII INPUT TIMING (1G)
T_setupR	TX data to clock input setup (Non-Delay Mode)	1			ns
T_holdR	TX clock to data input hold (Non-Delay Mode)	1			ns
	TX data to clock input setup (Delay Mode, 2ns delay)	-1			ns
	TX clock to data input hold (Delay Mode, 2ns delay)	3			ns
SMI TIMING
T1	MDC to MDIO (Output) Delay Time	0		10	ns
T2	MDIO (Input) to MDC Setup Time	10			ns
T3	MDIO (Input) to MDC Hold Time	10			ns
T4	MDC Frequency		2.5	25	MHz
OUTPUT CLOCK TIMING (25MHz clockout)
	Frequency (PPM)	-100		100	-
	Duty Cycle	40		60	%
	Rise Time			5000	ps
	Fall Time			5000	ps
	Frequency		25		MHz
	Jitter (Long Term)			375	ps
OUTPUT CLOCK TIMING (SyncE 125/5 MHz recovered clock)
	Frequency (PPM)	-100		100	ppm
	Duty Cycle	40		60	%
	Rise time			2500	ps
	Fall Time			2500	ps
	Jitter (Long Term)			1000	ps
25MHz INPUT CLOCK tolerance
	Frequency Tolerance	-100		+100	ppm
	Rise / Fall Time (10%-90%)			8	ns
	Jitter Tolerance (Accumulated : TIE over 100K cycles)		75		ps
	Duty Cycle	40		60	%
TRANSMIT LATENCY TIMING
Copper	RGMII to Cu (100M): Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI		169		ns
Copper	RGMII to Cu (1G): Roundtrip Latency (Transmit + Receive)			384	ns
RECEIVE LATENCY TIMING
Copper	Cu to RGMII (100M): SSD symbol on MDI to a) Rising edge of RX_DV with assertion of RX_CTRL b) Rising edge of RX_DV with assertion of RX_Dx		192		ns