ZHCSIS3B September 2018 – December 2022 DP83869HM
PRODUCTION DATA
The device incorporates an internal PRBS Built-In Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST can be performed using both internal loopback (digital or analog) or external loopback using a cable fixture. The BIST simulates pseudo-random data transfer scenarios in format of real packets and Inter-Packet Gap (IPG) on the lines. The BIST allows full control of the packet lengths and of the IPG.
The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for the BIST. The received data is compared to the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass or fail status. The number of error bytes that the PRBS checker received is stored in the PRBS_TX_CHK_CTRL register (39h). The status of whether the PRBS checker is locked to the incoming receive bit stream, whether the PRBS has lost sync, and whether the packet generator is busy, can be read from the GEN_STATUS2 register (17h). While the lock and sync indications are required to identify the beginning of proper data reception, for any link failures or data corruption, the best indication is the contents of the error counter in the PRBS_TX_CHK_CTRL register (39h). The number of received bytes are stored in PRBS_TX_CHK_BYTE_CNT (3Ah).
The PRBS test can be put in a continuous mode by using the BIST_CONTROL register (16h). In continuous mode, when one of the PRBS counters reaches the maximum value, the counter starts counting from zero again. PRBS mode is not applicable in Bridge Modes and should not be used.