ZHCSIS3B September   2018  – December 2022 DP83869HM

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  WoL (Wake-on-LAN) Packet Detection
        1. 9.3.1.1 Magic Packet Structure
        2. 9.3.1.2 Magic Packet Example
        3. 9.3.1.3 Wake-on-LAN Configuration and Status
      2. 9.3.2  Start of Frame Detect for IEEE 1588 Time Stamp
        1. 9.3.2.1 SFD Latency Variation and Determinism
          1. 9.3.2.1.1 1000-Mb SFD Variation in Master Mode
          2. 9.3.2.1.2 1000-Mb SFD Variation in Slave Mode
          3. 9.3.2.1.3 100-Mb SFD Variation
      3. 9.3.3  Clock Output
      4. 9.3.4  Loopback Mode
        1. 9.3.4.1 Near-End Loopback
          1. 9.3.4.1.1 MII Loopback
          2. 9.3.4.1.2 PCS Loopback
          3. 9.3.4.1.3 Digital Loopback
          4. 9.3.4.1.4 Analog Loopback
          5. 9.3.4.1.5 External Loopback
          6. 9.3.4.1.6 Far-End (Reverse) Loopback
        2.       39
      5. 9.3.5  BIST Configuration
      6. 9.3.6  Interrupt
      7. 9.3.7  Power-Saving Modes
        1. 9.3.7.1 IEEE Power Down
        2. 9.3.7.2 Active Sleep
        3. 9.3.7.3 Passive Sleep
      8. 9.3.8  Mirror Mode
      9. 9.3.9  Speed Optimization
      10. 9.3.10 Cable Diagnostics
        1. 9.3.10.1 TDR
      11. 9.3.11 Fast Link Drop
      12. 9.3.12 Jumbo Frames
    4. 9.4 Device Functional Modes
      1. 9.4.1  Copper Ethernet
        1. 9.4.1.1 1000BASE-T
        2. 9.4.1.2 100BASE-TX
        3. 9.4.1.3 10BASE-Te
      2. 9.4.2  Fiber Ethernet
        1. 9.4.2.1 1000BASE-X
        2. 9.4.2.2 100BASE-FX
      3. 9.4.3  Serial GMII (SGMII)
      4. 9.4.4  Reduced GMII (RGMII)
        1. 9.4.4.1 1000-Mbps Mode Operation
        2. 9.4.4.2 1000-Mbps Mode Timing
        3. 9.4.4.3 10- and 100-Mbps Mode
      5. 9.4.5  Media Independent Interface (MII)
      6. 9.4.6  Bridge Modes
        1. 9.4.6.1 RGMII-to-SGMII Mode
        2. 9.4.6.2 SGMII-to-RGMII Mode
        3.       69
      7. 9.4.7  Media Convertor Mode
      8. 9.4.8  Register Configuration for Operational Modes
        1. 9.4.8.1 RGMII-to-Copper Ethernet Mode
        2. 9.4.8.2 RGMII-to-1000Base-X Mode
        3. 9.4.8.3 RGMII-to-100Base-FX Mode
        4. 9.4.8.4 RGMII-to-SGMII Bridge Mode
        5. 9.4.8.5 1000M Media Convertor Mode
        6. 9.4.8.6 100M Media Convertor Mode
        7. 9.4.8.7 SGMII-to-Copper Ethernet Mode
      9. 9.4.9  Serial Management Interface
        1. 9.4.9.1 Extended Address Space Access
          1. 9.4.9.1.1 Write Address Operation
          2. 9.4.9.1.2 Read Address Operation
          3. 9.4.9.1.3 Write (No Post Increment) Operation
          4. 9.4.9.1.4 Read (No Post Increment) Operation
          5. 9.4.9.1.5 Write (Post Increment) Operation
          6. 9.4.9.1.6 Read (Post Increment) Operation
          7. 9.4.9.1.7 Example of Read Operation Using Indirect Register Access
          8. 9.4.9.1.8 Example of Write Operation Using Indirect Register Access
      10. 9.4.10 Auto-Negotiation
        1. 9.4.10.1 Speed and Duplex Selection - Priority Resolution
        2. 9.4.10.2 Master and Slave Resolution
        3. 9.4.10.3 Pause and Asymmetrical Pause Resolution
        4. 9.4.10.4 Next Page Support
        5. 9.4.10.5 Parallel Detection
        6. 9.4.10.6 Restart Auto-Negotiation
        7. 9.4.10.7 Enabling Auto-Negotiation Through Software
        8. 9.4.10.8 Auto-Negotiation Complete Time
        9. 9.4.10.9 Auto-MDIX Resolution
    5. 9.5 Programming
      1. 9.5.1 Strap Configuration
        1. 9.5.1.1 Straps for PHY Address
        2. 9.5.1.2 Strap for DP83869HM Functional Mode Selection
        3. 9.5.1.3 LED Default Configuration Based on Device Mode
        4. 9.5.1.4 Straps for RGMII/SGMII to Copper
        5. 9.5.1.5 Straps for RGMII to 1000Base-X
        6. 9.5.1.6 Straps for RGMII to 100Base-FX
        7. 9.5.1.7 Straps for Bridge Mode (SGMII-RGMII)
        8. 9.5.1.8 Straps for 100M Media Convertor
        9. 9.5.1.9 Straps for 1000M Media Convertor
      2. 9.5.2 LED Configuration
      3. 9.5.3 Reset Operation
        1. 9.5.3.1 Hardware Reset
        2. 9.5.3.2 IEEE Software Reset
        3. 9.5.3.3 Global Software Reset
        4. 9.5.3.4 Global Software Restart
    6. 9.6 Register Maps
      1. 9.6.1 DP83869 Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Copper Ethernet Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Clock Input
            1. 10.2.1.2.1.1 Crystal Recommendations
            2. 10.2.1.2.1.2 External Clock Source Recommendation
          2. 10.2.1.2.2 Magnetics Requirements
            1. 10.2.1.2.2.1 Magnetics Connection
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Fiber Ethernet Typical Ethernet
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Transceiver Connections
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Two-Supply Configuration
    2. 11.2 Three-Supply Configuration
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
        1. 12.1.1.1 MAC Interface Layout Guidelines
          1. 12.1.1.1.1 SGMII Layout Guidelines
          2. 12.1.1.1.2 RGMII Layout Guidelines
        2. 12.1.1.2 MDI Layout Guidelines
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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8.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1000Base-X/100Base-FX/SGMII INPUT
Input differential voltage tolerance SI_P and SI_N, AC coupled 0.3 0.5 2.0 V
Receiver differential input impedance (DC) 80 100 120 Ohm
Frequency tolerance SI_P and SI_N, AC coupled -100 +100 ppm
1000Base-X OUTPUT
Clock signal duty cycle SO_P and SO_N, AC coupled, 0101010101 pattern 48 52 %
Vod fall time (20%-80%) SO_P and SO_N, AC coupled, 0101010101 pattern 100 200 ps
Vod rise time (20%-80%) SO_P and SO_N, AC coupled, 0101010101 pattern 100 200 ps
Total Ouput Jitter SO_P and SO_N, AC coupled 192 ps
Output Differential Voltage (Configuration bits for 0.6V - 1.27V; Default at 1.1V) SO_P and SO_N, AC coupled 1060 1100 1140 mV
100Base-FX OUTPUT
Clock signal duty cycle at 625MHz SO_P and SO_N, AC coupled 55 %
Vod fall time (20%-80%) SO_P and SO_N, AC coupled 330 ps
Vod rise time (20%-80%) SO_P and SO_N, AC coupled 330 ps
Jitter SO_P and SO_N, AC coupled 192 ps
Output Differential Voltage (Configuration bits for 0.6V - 1.8V) SO_P and SO_N, AC coupled 450 910 mV
SGMII OUTPUT
Clock signal duty cycle @625MHz SO_P and SO_N, AC coupled, 0101010101 pattern 48 52 %
Vod fall time (20%-80%) SO_P and SO_N, AC coupled, 0101010101 pattern 100 200 ps
Vod rise time (20%-80%) SO_P and SO_N, AC coupled, 0101010101 pattern 100 200 ps
Output Jitter SO_P and SO_N, AC coupled 300 ps
Output Differential Voltage (Configuration bits for 0.6V - 1.27V; Default at 1.1V) SO_P and SO_N, AC coupled 1060 1100 1140 mV
IEEE Tx CONFORMANCE (1000BaseT)
Output Differential Voltage Normal Mode, All channels 0.67 0.745 0.82 V
IEEE Tx CONFORMANCE (100BaseTx)
Output Differential Voltage Normal Mode, Channels A and B 0.95 1.00 1.05 V
IEEE Tx CONFORMANCE (10BaseTe)
Output Differential Voltage 1.75 V
POWER CONSUMPTION Copper mode (100m cable)
Total RGMII to Copper (1G) Room Temperature, Nominal supply voltages 483 mW
RGMII to Copper (100M) 215 mW
RGMII to Copper (10M) 260 mW
MII to Copper (100M) 212 mW
MII to Copper (10M) 261 mW
SGMII to Copper (1G) 496 mW
SGMII to Copper (100M) 251 mW
SGMII to Copper (10M) 294 mW
I(1V1) RGMII to Copper (1G) Room Temperature, 1.1V supply voltage 131 195 mA
RGMII to Copper (100M) 47 110 mA
RGMII to Copper (10M) 37 100 mA
MII to Copper (100M) 43 110 mA
MII to Copper (10M) 36 95 mA
SGMII to Copper (1G) 141 220 mA
SGMII to Copper (100M) 60 125 mA
SGMII to Copper (10M) 50 112 mA
I(1V8) RGMII to Copper (1G) Room Temperature, 1.8V supply voltage 52 55 mA
RGMII to Copper (100M) 21 26 mA
RGMII to Copper (10M) 11 15 mA
MII to Copper (100M) 21 26 mA
MII to Copper (10M) 10 15 mA
SGMII to Copper (1G) 55 60 mA
SGMII to Copper (100M) 24 28 mA
SGMII to Copper (10M) 14 18 mA
I(2V5) RGMII to Copper (1G) Room Temperature, 2.5V supply voltage 86 100 mA
RGMII to Copper (100M) 46 50 mA
RGMII to Copper (10M) 76 90 mA
MII to Copper (100M) 45 52 mA
MII to Copper (10M) 78 92 mA
SGMII to Copper (1G) 93 100 mA
SGMII to Copper (100M) 53 58 mA
SGMII to Copper (10M) 82 95 mA
I(VDDIO=3.3V) RGMII to Copper (1G) Room Temperature, 3.3V supply voltage 30 80 mA
RGMII to Copper (100M) 13 22 mA
RGMII to Copper (10M) 10 16 mA
MII to Copper (100M) 15 66 mA
MII to Copper (10M) 11 38 mA
SGMII to Copper (1G) 10 16 mA
SGMII to Copper (100M) 10 16 mA
SGMII to Copper (10M) 10 16 mA
I(VDDIO=1.8V) RGMII to Copper (1G) Room Temperature, 1.8V supply voltage 17 30 mA
RGMII to Copper (100M) 6 12 mA
RGMII to Copper (10M) 5 10 mA
MII to Copper (100M) 8 15 mA
MII to Copper (10M) 5 10 mA
SGMII to Copper (1G) 5 10 mA
SGMII to Copper (100M) 5 10 mA
SGMII to Copper (10M) 5 10 mA
POWER CONSUMPTION Fiber mode 
Total RGMII to 1000Base-X Room Temperature, Nominal supply voltages 142 mW
RGMII to 100Base-FX 111 mW
MII to 100Base-FX 107 mW
I(1V1) RGMII to 1000Base-X Room Temperature, 1.1V supply voltage 52 mA
RGMII to 100Base-FX 44 mA
MII to 100Base-FX 41.8 mA
I(1V8) RGMII to 1000Base-X Room Temperature, 1.8V supply voltage 14 mA
RGMII to 100Base-FX 14 mA
MII to 100Base-FX 12 mA
I(2V5) RGMII to 1000Base-X Room Temperature, 2.5V supply voltage 11 mA
RGMII to 100Base-FX 10 mA
MII to 100Base-FX 10 mA
I(VDDIO=3.3V) RGMII to 1000Base-X Room Temperature, 3.3V supply voltage 32 mA
RGMII to 100Base-FX 14 mA
MII to 100Base-FX 16 mA
I(VDDIO=1.8V) RGMII to 1000Base-X Room Temperature, 1.8V supply voltage 18 mA
RGMII to 100Base-FX 7 mA
MII to 100Base-FX 8 mA
POWER CONSUMPTION R2S mode  
Total RGMII to SGMII (1G) Room Temperature, Nominal supply voltages 142 mW
RGMII to SGMII (100M) 120 mW
RGMII to SGMII (10M) 117 mW
I(1V1) RGMII to SGMII (1G) Room Temperature, 1.1V supply voltage 52 mA
RGMII to SGMII (100M) 50 mA
RGMII to SGMII (10M) 49 mA
I(1V8) RGMII to SGMII (1G) Room Temperature, 1.8V supply voltage 14 mA
RGMII to SGMII (100M) 13 mA
RGMII to SGMII (10M) 14 mA
I(2V5) RGMII to SGMII (1G) Room Temperature, 2.5V supply voltage 11 mA
RGMII to SGMII (100M) 11 mA
RGMII to SGMII (10M) 11 mA
I(VDDIO=3.3V) RGMII to SGMII (1G) Room Temperature, 3.3V supply voltage 32 mA
RGMII to SGMII (100M) 15 mA
RGMII to SGMII (10M) 12 mA
I(VDDIO=1.8V) RGMII to SGMII (1G) Room Temperature, 1.8V supply voltage 18 mA
RGMII to SGMII (100M) 8 mA
RGMII to SGMII (10M) 6 mA
POWER CONSUMPTION S2R mode 
Total SGMII to RGMII (1G) Room Temperature, Nominal supply voltages 142 mW
SGMII to RGMII (100M) 121 mW
SGMII to RGMII (10M) 117 mW
I(1V1) SGMII to RGMII (1G) Room Temperature, 1.1V supply voltage 52 mA
SGMII to RGMII (100M) 49 mA
SGMII to RGMII (10M) 49 mA
I(1V8) SGMII to RGMII (1G) Room Temperature, 1.8V supply voltage 14 mA
SGMII to RGMII (100M) 14 mA
SGMII to RGMII (10M) 14 mA
I(2V5) SGMII to RGMII (1G) Room Temperature, 2.5V supply voltage 11 mA
SGMII to RGMII (100M) 11 mA
SGMII to RGMII (10M) 11 mA
I(VDDIO=3.3V) SGMII to RGMII (1G) Room Temperature, 3.3V supply voltage 33 mA
SGMII to RGMII (100M) 16 mA
SGMII to RGMII (10M) 13 mA
I(VDDIO=1.8V) SGMII to RGMII (1G) Room Temperature, 1.8V supply voltage 18 mA
SGMII to RGMII (100M) 8 mA
SGMII to RGMII (10M) 6 mA
POWER CONSUMPTION Cu-Fiber mode (100m cable)
Total 1000Base-TX to 1000Base-FX Room Temperature, Nominal supply voltage 495 mW
100Base-TX to 100Base-FX 243 mW
I(1V1) 1000Base-TX to 1000Base-FX Room Temperature, 1.1V supply voltage 142 mA
100Base-TX to 100Base-FX 55 mA
I(1V8) 1000Base-TX to 1000Base-FX Room Temperature, 1.8V supply voltage 55 mA
100Base-TX to 100Base-FX 24 mA
I(2V5) 1000Base-TX to 1000Base-FX Room Temperature, 2.5V supply voltage 93 mA
100Base-TX to 100Base-FX 52 mA
I(VDDIO=3.3V) 1000Base-TX to 1000Base-FX Room Temperature, 3.3V supply voltage 9 mA
100Base-TX to 100Base-FX 10 mA
I(VDDIO=1.8V) 1000Base-TX to 1000Base-FX Room Temperature, 1.8V supply voltage 4 mA
100Base-TX to 100Base-FX 5 mA
POWER CONSUMPTION Low power modes
Total IEEE Power Down Room Temperature, Nominal Voltages 76 mW
Active Sleep 165 mW
RESET 82 mW
BOOTSTRAP DC CHARACTERISTICS (4 Level) (PHY address pins)
VMODE0 Mode 0 Strap Voltage Range 0 0.093 x VDDIO V
VMODE1 Mode 1 Strap Voltage Range 0.136 x VDDIO 0.184 x VDDIO V
VMODE2 Mode 2 Strap Voltage Range 0.219 x VDDIO 0.280 x VDDIO V
VMODE3 Mode 3 Strap Voltage Range 0.6 x VDDIO 0.888 x VDDIO V
BOOTSTRAP DC CHARACTERISTICS (2 Level)
VMODE0 Mode 0 Strap Voltage Range  0 0.18 x VDDIO V
VMODE1 Mode 1 Strap Voltage Range 0.5 x VDDIO 0.88 x VDDIO V
IO CHARACTERISTICS
VIH High Level Input Voltage VDDIO = 3.3V ±5% 2 V
VIL Low Level Input Voltage VDDIO = 3.3V ±5% 0.8 V
VOH High Level Output Voltage IOH = -2mA, VDDIO = 3.3V ±5% 2.4 V
VOL Low Level Output Voltage IOL = 2mA, VDDIO = 3.3V ±5% 0.4 V
VIH High Level Input Voltage VDDIO = 2.5V ±5% 1.7 V
VIL Low Level Input Voltage VDDIO = 2.5V ±5% 0.7 V
VOH High Level Output Voltage IOH = -2mA, VDDIO = 2.5V ±5% 2 V
VOL Low Level Output Voltage IOL = 2mA, VDDIO = 2.5V ±5% 0.4 V
VIH High Level Input Voltage VDDIO = 1.8V ±5% 0.65*VDDIO V
VIL Low Level Input Voltage VDDIO = 1.8V ±5% 0.35*VDDIO V
VOH High Level Output Voltage IOH = -2mA, VDDIO = 1.8V ±5% VDDIO-0.45 V
VOL Low Level Output Voltage IOL = 2mA, VDDIO = 1.8V ±5% 0.45 V
IIH Input High Current TA = -40℃ to 125℃, VIN=VDDIO -20 20 µA
IIL Input Low Current TA = -40℃ to 125℃, VIN=GND -20 20 µA
Iozh Tri-state Output High Current TA = -40℃ to 125℃, VOUT=VDDIO -20 20 µA
Iozl Tri-state Output Low Current TA = -40℃ to 125℃, VOUT=GND -20 20 µA
Rpulldn Internal Pull Down Resistor 6.75 9 11.25 kΩ
XI VIH High Level Input Voltage 1.2 VDDIO V
XI VIL Low Level Input Voltage 0.6 V
CIN Input Capacitance XI 1 pF
CIN Input Capacitance INPUT PINS 5 pF
COUT Output Capacitance XO 1 pF
COUT Output Capacitance OUTPUT PINS 5 pF
Rseries Integrated MAC Series Termination Resistor RX_D[3:0], RX_ER, RX_DV, RX_CLK 50 Ω