ZHCSIS3B September 2018 – December 2022 DP83869HM
PRODUCTION DATA
Figure 11-3 shows the connection diagram for the three-supply configuration.
Place 1-μF and 0.1-μF decoupling capacitors as close as possible to component VDD pins, placing the 0.1-μF capacitor closest to the pin.
The strap (SUPPLYMODE_SEL, pin 23) shall be pulled high to set triple-supply mode. VDDIO may be 3.3 V, 2.5 V, or 1.8 V. VDDIO strap shall be selected appropriately to VDDIO voltage applied.
For three-supply configuration, the recommendation is to power all supplies together. If that is not possible, then the following power sequencing must be used.
PARAMETER | TEST CONDITIONS |
MIN |
NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
t1 | Supply ramp time | Applicable to all supplies | 0.5 | 100 | ms | |
t2 | Time instance at which VDDIO starts up | Measured with respect to start of VDDA2P5 and VDD1P1 | 0 | 50 | ms | |
t3 | Time instance at which VDDA1P8_x starts up | Measured with respect to start of VDDA2P5 and VDD1P1 | 0 | 50 | ms |