ZHCSIS3C
September 2018 – April 2024
DP83869HM
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Timing Diagrams
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
WoL (Wake-on-LAN) Packet Detection
7.3.1.1
Magic Packet Structure
7.3.1.2
Wake-on-LAN Configuration and Status
7.3.2
Start of Frame Detect for IEEE 1588 Time Stamp
7.3.2.1
SFD Latency Variation and Determinism
7.3.2.1.1
1000Mb SFD Variation in Master Mode
7.3.2.1.2
1000Mb SFD Variation in Slave Mode
7.3.2.1.3
100-Mb SFD Variation
7.3.3
Clock Output
7.3.4
Loopback Mode
7.3.4.1
Near-End Loopback
7.3.4.1.1
MII Loopback
7.3.4.1.2
PCS Loopback
7.3.4.1.3
Digital Loopback
7.3.4.1.4
Analog Loopback
7.3.4.1.5
External Loopback
7.3.4.1.6
Far-End (Reverse) Loopback
37
7.3.5
BIST Configuration
7.3.6
Interrupt
7.3.7
Power-Saving Modes
7.3.7.1
IEEE Power Down
7.3.7.2
Active Sleep
7.3.7.3
Passive Sleep
7.3.8
Mirror Mode
7.3.9
Speed Optimization
7.3.10
Cable Diagnostics
7.3.10.1
TDR
7.3.11
Fast Link Drop
7.3.12
Jumbo Frames
7.4
Device Functional Modes
7.4.1
Copper Ethernet
7.4.1.1
1000BASE-T
7.4.1.2
100BASE-TX
7.4.1.3
10BASE-Te
7.4.2
Fiber Ethernet
7.4.2.1
1000BASE-X
7.4.2.2
100BASE-FX
7.4.3
Serial GMII (SGMII)
7.4.4
Reduced GMII (RGMII)
7.4.4.1
1000Mbps Mode Operation
7.4.4.2
1000Mbps Mode Timing
7.4.4.3
10 and 100Mbps Mode
7.4.5
Media Independent Interface (MII)
7.4.6
Bridge Modes
7.4.6.1
RGMII-to-SGMII Mode
7.4.6.2
SGMII-to-RGMII Mode
67
7.4.7
Media Convertor Mode
7.4.8
Register Configuration for Operational Modes
7.4.8.1
RGMII-to-Copper Ethernet Mode
7.4.8.2
RGMII-to-1000Base-X Mode
7.4.8.3
RGMII-to-100Base-FX Mode
7.4.8.4
RGMII-to-SGMII Bridge Mode
7.4.8.5
1000M Media Convertor Mode
7.4.8.6
100M Media Convertor Mode
7.4.8.7
SGMII-to-Copper Ethernet Mode
7.4.9
Serial Management Interface
7.4.9.1
Extended Register Space Access
7.4.9.1.1
Read (No Post Increment) Operation
7.4.9.1.2
Write (No Post Increment) Operation
7.4.10
Auto-Negotiation
7.4.10.1
Speed and Duplex Selection - Priority Resolution
7.4.10.2
Master and Slave Resolution
7.4.10.3
Pause and Asymmetrical Pause Resolution
7.4.10.4
Next Page Support
7.4.10.5
Parallel Detection
7.4.10.6
Restart Auto-Negotiation
7.4.10.7
Enabling Auto-Negotiation Through Software
7.4.10.8
Auto-Negotiation Complete Time
7.4.10.9
Auto-MDIX Resolution
7.5
Programming
7.5.1
Strap Configuration
7.5.1.1
Straps for PHY Address
7.5.1.2
Strap for DP83869HM Functional Mode Selection
7.5.1.3
LED Default Configuration Based on Device Mode
7.5.1.4
Straps for RGMII/SGMII to Copper
7.5.1.5
Straps for RGMII to 1000Base-X
7.5.1.6
Straps for RGMII to 100Base-FX
7.5.1.7
Straps for Bridge Mode (SGMII-RGMII)
7.5.1.8
Straps for 100M Media Convertor
7.5.1.9
Straps for 1000M Media Convertor
7.5.2
LED Configuration
7.5.3
Reset Operation
7.5.3.1
Hardware Reset
7.5.3.2
IEEE Software Reset
7.5.3.3
Global Software Reset
7.5.3.4
Global Software Restart
7.6
Register Maps
7.6.1
DP83869 Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Copper Ethernet Typical Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Clock Input
8.2.1.2.1.1
Crystal Recommendations
8.2.1.2.1.2
External Clock Source Recommendation
8.2.1.2.2
Magnetics Requirements
8.2.1.2.2.1
Magnetics Connection
8.2.1.3
Application Curves
8.2.2
Fiber Ethernet Typical Ethernet
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
Transceiver Connections
8.2.2.3
Application Curves
8.3
Power Supply Recommendations
8.3.1
Two-Supply Configuration
8.3.2
Three-Supply Configuration
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
Signal Traces
8.4.1.1.1
MAC Interface Layout Guidelines
8.4.1.1.1.1
SGMII Layout Guidelines
8.4.1.1.1.2
RGMII Layout Guidelines
8.4.1.1.2
MDI Layout Guidelines
8.4.1.2
Return Path
8.4.1.3
Transformer Layout
8.4.1.4
Metal Pour
8.4.1.5
PCB Layer Stacking
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
支持资源
9.4
Trademarks
9.5
静电放电警告
9.6
术语表
10
Revision History
11
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
RGZ|48
MPQF123F
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsis3c_oa
zhcsis3c_pm
1
特性
多种工作模式
支持媒介:铜缆和光纤
可在铜缆和光纤之间进行切换
在 RGMII 与 SGMII 之间建立桥接
可用的最高环境温度为 125°C
超过 8kV IEC61000-4-2 ESD
低功耗
对于 1000Base-X,< 150mW
对于 1000Base-T,< 500mW
低 RGMII 延迟
对于 1000Base-T,总延迟 ≤ 384ns
对于 100Base-TX,总延迟 ≤ 361ns
符合时间敏感网络 (TSN) 标准
适用于 SyncE 的恢复时钟输出
可选同步时钟输出:25MHz 和 125MHz
SFF-8431 V4.1、1000BASE-X 和 100BASE-FX 兼容
通过 SFD 支持 IEEE1588
支持局域网唤醒
可配置的 IO 电压:1.8V、2.5V 和 3.3V
SGMII、RGMII、MII MAC 接口
巨型帧支持 1000M 和 100M 速度
电缆诊断
TDR
BIST
可编程 RGMII 终端阻抗
集成 MDI 终端电阻器
快速链路丢弃模式
符合 IEEE 802.3 1000Base-T、100Base-TX、10Base-Te、1000Base-X、100Base-FX 标准