ZHCSKM7G december   2019  – july 2023 DP83826E , DP83826I

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Mode Comparison Tables
  7. 6 Pin Configuration and Functions (ENHANCED Mode)
  8. 7 Pin Configuration and Functions (BASIC Mode)
  9. 8 Specifications
    1. 8.1 绝对最大额定值
    2. 8.2 ESD 等级
    3. 8.3 建议运行条件
    4. 8.4 热性能信息
    5. 8.5 电气特性
    6. 8.6 时序要求
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 9.3.2  Auto-MDIX Resolution
      3. 9.3.3  Energy Efficient Ethernet
        1. 9.3.3.1 EEE Overview
        2. 9.3.3.2 EEE Negotiation
      4. 9.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 9.3.5  Wake-on-LAN Packet Detection
        1. 9.3.5.1 Magic Packet Structure
        2. 9.3.5.2 Magic Packet Example
        3. 9.3.5.3 Wake-on-LAN Configuration and Status
      6. 9.3.6  Low Power Modes
        1. 9.3.6.1 Active Sleep
        2. 9.3.6.2 IEEE Power-Down
        3. 9.3.6.3 Deep Power Down State
      7. 9.3.7  RMII Repeater Mode
      8. 9.3.8  Clock Output
      9. 9.3.9  Media Independent Interface (MII)
      10. 9.3.10 Reduced Media Independent Interface (RMII)
      11. 9.3.11 Serial Management Interface
        1. 9.3.11.1 Extended Register Space Access
        2. 9.3.11.2 Write Address Operation
        3. 9.3.11.3 Read Address Operation
        4. 9.3.11.4 Write (No Post Increment) Operation
        5. 9.3.11.5 Read (No Post Increment) Operation
        6. 9.3.11.6 Example Write Operation (No Post Increment)
      12. 9.3.12 100BASE-TX
        1. 9.3.12.1 100BASE-TX Transmitter
          1. 9.3.12.1.1 Code-Group Encoding and Injection
          2. 9.3.12.1.2 Scrambler
          3. 9.3.12.1.3 NRZ to NRZI Encoder
          4. 9.3.12.1.4 Binary to MLT-3 Converter
        2. 9.3.12.2 100BASE-TX Receiver
      13. 9.3.13 10BASE-Te
        1. 9.3.13.1 Squelch
        2. 9.3.13.2 Normal Link Pulse Detection and Generation
        3. 9.3.13.3 Jabber
        4. 9.3.13.4 Active Link Polarity Detection and Correction
      14. 9.3.14 Loopback Modes
        1. 9.3.14.1 Near-end Loopback
        2. 9.3.14.2 MII Loopback
        3. 9.3.14.3 PCS Loopback
        4. 9.3.14.4 Digital Loopback
        5. 9.3.14.5 Analog Loopback
        6. 9.3.14.6 Far-End (Reverse) Loopback
      15. 9.3.15 BIST Configurations
      16. 9.3.16 Cable Diagnostics
        1. 9.3.16.1 Time Domain Reflectometry (TDR)
        2. 9.3.16.2 Fast Link-Drop Functionality
      17. 9.3.17 LED and GPIO Configuration
    4. 9.4 Programming
      1. 9.4.1 Hardware Bootstraps Configuration
        1. 9.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)
          1. 9.4.1.1.1 Bootstraps for PHY Address
        2. 9.4.1.2 DP83826 Strap Configuration (BASIC Mode)
          1. 9.4.1.2.1 Bootstraps for PHY Address
    5. 9.5 Register Maps
      1. 9.5.1 DP83826 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 10.2.2 Transformer Recommendations
      3. 10.2.3 Capacitive DC Blocking
      4. 10.2.4 Design Requirements
        1. 10.2.4.1 Clock Requirements
          1. 10.2.4.1.1 Oscillator
          2. 10.2.4.1.2 Crystal
      5. 10.2.5 Detailed Design Procedure
        1. 10.2.5.1 MII Layout Guidelines
        2. 10.2.5.2 RMII Layout Guidelines
        3. 10.2.5.3 MDI Layout Guidelines
      6. 10.2.6 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
        1. 12.1.5.1 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  15. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.3.16.2 Fast Link-Drop Functionality

The DP83826 includes advanced link-drop capabilities that support various real-time applications. The link-drop mechanism is configurable and includes enhanced modes that allow extremely fast link-drop reaction times.

The DP83826 supports an enhanced link-drop mechanism, also called fast link-drop (FLD), which shortens the observation window for determining link. There are multiple ways of determining link status, which can be enabled or disabled based on user preference.

Depending on what mode the DP83826 is in, the default state of FLD will differ. In ENHANCED mode, FLD and all its detection mechanisms are disabled by default through pulling down Strap7. For EtherCAT applications or applications with Fast link drop enabled and expect to handle Baseline wander packets, it is recommended to disable signal energy detect, which can be done by setting Strap8. The table below summarizes the modes enabled by strap.

Table 9-5 FLD Detection Modes by Strap
Strap ConfigurationRX Error CountMLT3 Error CountLow SNR ThresholdSignal/Energy LossDescrambler Link Loss

(Default)

Strap7 = LOW

Strap1 = X

Strap8 = X

DisabledDisabledDisabledDisabledDisabled
Strap7 = HIGH

Strap1 = HIGH

Strap8 = LOW

EnabledEnabledEnabledEnabled
Strap7 = HIGH

Strap1 = LOW

Strap8 = LOW

EnabledDisabledEnabledDisabled
Strap7 = HIGH

Strap1 = LOW

Strap8 = HIGH

EnabledDisabledDisabledDisabled

In BASIC mode, fast link-drop is enabled by default. The default mechanisms in BASIC mode will be RX error and signal/energy loss.

In both modes, FLD can be configured using the Control Register #3 (CR3, register address 0x000B). Bits[3:0] and bit[10] allow for various FLD conditions to be enabled. When link-drop occurs, indication of a particular fault condition can be read from the Fast Link Drop Status Register (FLDS, register address 0x000F).

GUID-F8C091B0-980F-4615-A913-A9E3CCDAB789-low.gifFigure 9-8 Fast Link-Drop

Fast link-drop criteria include:

  • RX error count - when a predefined number of 32 RX_ERs occur in a 10-μs window, the link is dropped.
  • MLT3 error count - when a predefined number of 20 MLT3 errors occur in a 10-μs window, the link is dropped. To use the MLT3 error based FLD, please configure register Fast Link Drop Config Register 1 (FLDCFG1, register address 0x0117) to 0x0417.
  • Low SNR threshold - when a predefined number of 20 threshold crossings occur in a 10-μs window, the link is dropped.
  • Signal/energy loss - when the energy detector indicates energy loss, the link is dropped.
  • Descrambler link loss - when the Descrambler loses lock, the link is dropped. To use the Descrambler link loss based FLD, please configure bits[5:0] of Fast Link Drop Config Register 2 (FLDCFG2, register address 0x0131) to 0x08.

The fast link-drop functionality allows the use of each of these options separately or in any combination.