ZHCSNO0B April 2021 – November 2021 DP83561-SP
PRODUCTION DATA
The DP83561-SP has several internal clocks, including the local reference clock, the Ethernet transmit clock, and the Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock. The local reference clock acts as the central source for all clocking in the device.
The local reference clock is embedded into the transmit network packet traffic and is recovered from the network packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream and is locked to the transmit clock in the partner.
Using the I/O Configuration register (address 0x170), the DP83561-SP can be configured to output these internal clocks through the CLK_OUT pin. For the I/O Configuration register (address 0x170) settings to work, an additional configuration of writing register 0x00C6 to value of 0x0010 is required. By default, the output clock is synchronous to the XI oscillator / crystal input. The default output clock is suitable for use as the reference clock of another DP83561-SP device. Through registers, the output clock can be configured to be synchronous to the receive data at the 125-MHz data rate or at the divide by 5 rate of 25 MHz. It can also be configured to output the line driver transmit clock. When operating in 1000Base-T mode, the output clock can be configured for any of the four transmit or receive channels.
It is important to note that when the clock output of DP83561-SP is used as a clock input for another device, for example two DP83561-SP devices in a daisy chain, then the primary DP838561-SP should not be reset through the RESET pin. If reset is required then it should be performed through the software. The output clock can be disabled using the CLK_O_DISABLE bit of the I/O Configuration register.