ZHCSNO0B April 2021 – November 2021 DP83561-SP
PRODUCTION DATA
The DP83561-SP implements an ECC scheme for the configuration registers to detect SEFI events. If any change in the configuration registers are detected or corrected by the ECC, an interrupt will be raised for indication to the higher level system. Status is indicated by the PHY on register 0x01D8 bits[15:12]. To enable ECC, refer to register 0x1EE bits[9:7].
During POR, or on the rising edge of SMI_DISABLE signal, the DP83561-SP will calculate a checksum of the bits in all configuration registers sequentially by address. The resulting checksum will then be stored in SEFI immune memory as value CHECKSUM_VALUE.
While SMI_DISABLE signal remains asserted, the DP83561-SP will continuously calculate the checksum for all configuration registers, kept as CHECKSUM_CHK. If CHECKSUM_VALUE and CHECKSUM_CHK ever differ, the INT_ECC_N signal will be asserted.
When SMI_DISABLE signal is deasserted, the CHECKSUM_VALUE will be cleared and the checksum function will not be performed on the configuration registers.
When the AUTO_RECOVER bit is set, the configuration registers will be reset to default values including the currently selected pin options. The INT_ECC_N signal will be asserted regardless of AUTO_RECOVER setting.