ZHCSNO0B 数据表 | 德州仪器 TI.com.cn

Table 7-10 lists the DP83561SP registers. All register offset addresses not listed in Table 7-10 should be considered as reserved locations and the register contents should not be modified.

Table 7-10 DP83561SP Registers

Offset	Acronym	Register Name	Section
0x0	BMCR	Basic Mode Control Register	Go
0x1	BMSR	Basic Mode Status Register	Go
0x2	PHYIDR1	PHY Identifier Register #1	Go
0x3	PHYIDR2	PHY Identifier Register #2	Go
0x4	ANAR	Auto-Negotiation Advertisement Register	Go
0x5	ALNPAR	Auto-Negotiation Link Partner Ability Register	Go
0x6	ANER	Auto-Negotiate Expansion Register	Go
0x7	ANNPTR	Auto-Negotiation Next Page Transmit Register	Go
0x8	ANLNPTR	Auto-Negotiation Link Partner Next Page Receive Register	Go
0x9	GEN_CFG1	Configuration Register 1	Go
0xA	GEN_STATUS1	Status Register 1	Go
0xD	REGCR	Register Control Register	Go
0xE	ADDAR	Address or Data Register	Go
0xF	1KSCR	1000BASE-T Status Register	Go
0x10	PHY_CONTROL	PHY Control Register	Go
0x11	PHY_STATUS	PHY Status Register	Go
0x12	INTERRUPT_MASK	MII Interrupt Control Register	Go
0x13	INTERRUPT_STATUS	Interrupt Status Register	Go
0x14	GEN_CFG2	Configuration Register 2	Go
0x15	RX_ERR_CNT		Go
0x16	BIST_CONTROL	BIST Control Register	Go
0x17	GEN_STATUS2	Status Register 2	Go
0x18	LEDS_CFG1	LED Configuration Register 1	Go
0x19	LEDS_CFG2	LED Configuration Register 2	Go
0x1A	LEDS_CFG3	LED Configuration Register 3	Go
0x1E	GEN_CFG4	Configuration Register 3	Go
0x1F	GEN_CTRL	Control Register	Go
0x25	ANALOG_TEST_CTRL	Testmode Channel Control Register	Go
0x2C	GEN_CFG_ENH_AMIX		Go
0x2D	GEN_CFG_FLD		Go
0x2E	GEN_CFG_FLD_THR		Go
0x31	GEN_CFG3	Configuration Register 4	Go
0x32	RGMII_CTRL	RGMII Control Register	Go
0x33	RGMII_CTRL2		Go
0x39	PRBS_TX_CHK_CTRL		Go
0x3A	PRBS_TX_CHK_BYTE_CNT		Go
0x43	G_100BT_REG0		Go
0x55	G_1000BT_PMA_STATUS	Skew FIFO Status Register	Go
0x6E	STRAP_STS	Strap Status Register	Go
0x71	DBG_PRBS_BYTE_CNT		Go
0x72	DBG_PRBS_ERR_CNT		Go
0x7B	DBG_PKT_LEN_PRBS		Go
0x86	ANA_RGMII_DLL_CTRL	RGMII Delay Control Register	Go
0xC6	ANA_PLL_PROG_PI		Go
0xFE	LOOPCR	Loopback Configuration Register	Go
0x134	RXF_CFG		Go
0x135	RXF_STATUS		Go
0x170	IO_MUX_CFG		Go
0x180	TDR_GEN_CFG1		Go
0x181	TDR_GEN_CFG2		Go
0x182	TDR_SEG_DURATION1		Go
0x183	TDR_SEG_DURATION2		Go
0x184	TDR_GEN_CFG3		Go
0x185	TDR_GEN_CFG4		Go
0x190	TDR_PEAKS_LOC_A_0_1		Go
0x191	TDR_PEAKS_LOC_A_2_3		Go
0x192	TDR_PEAKS_LOC_A_4_B_0		Go
0x193	TDR_PEAKS_LOC_B_1_2		Go
0x194	TDR_PEAKS_LOC_B_3_4		Go
0x195	TDR_PEAKS_LOC_C_0_1		Go
0x196	TDR_PEAKS_LOC_C_2_3		Go
0x197	TDR_PEAKS_LOC_C_4_D_0		Go
0x198	TDR_PEAKS_LOC_D_1_2		Go
0x199	TDR_PEAKS_LOC_D_3_4		Go
0x1A4	TDR_GEN_STATUS		Go
0x1A5	TDR_PEAKS_SIGN_A_B		Go
0x1A6	TDR_PEAKS_SIGN_C_D		Go
0x1D6	MASK_SOFT_RST		Go
0x1D7	MASK_EXTERNAL_INT		Go
0x1D8	SEU_STATUS_REG		Go
0x1D9	REF_CLK_PPM_MONITOR_CNT		Go
0x1DA	MON_CLK_PPM_MONITOR_CNT		Go
0x1DB	MAX_PLUS_PPM_MON_CNT		Go
0x1DC	MAX_MINUS_PPM_MON_CNT		Go
0x1DD	SYS_CLK_PPM_STATUS		Go
0x1DE	PLL_CLK_PPM_STATUS		Go
0x1DF	OP_MODE_DECODE		Go
0x1E0	GPIO_MUX_CTRL		Go
0x1E2	MONITOR_REGISTERS_0		Go
0x1E7	MONITOR_REGISTERS_1		Go
0x1E8	MONITOR_REGISTERS_2		Go
0x1E9	MONITOR_REGISTERS_3		Go
0x1EA	MONITOR_REGISTERS_RD_0		Go
0x1EE	LOCK_DET_REG		Go

Complex bit access types are encoded to fit into small table cells. Table 7-11 shows the codes that are used for access types in this section.

Table 7-11 DP83561SP Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	R C	Read to Clear
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
W1C	W 1C	Write 1 to clear
WoP	W	Write
WtoP	W	Write
Reset or Default Value
- n		Value after reset or the default value

7.6.1.1 BMCR Register (Offset = 0x0) [Reset = 0x1140]

BMCR is shown in Table 7-12.

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IEEE defined register to control PHY functionality.

Table 7-12 BMCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESET	R/W	0x0	This bit controls the MII reset function. This bit is self cleared after reset is completed. 0x0 = Normal Operation 0x1 = Reset.
14	MII_LOOPBACK	R/W	0x0	This bit controls the MII Loopback. When enabled, this will send data back to the MAC 0x0 = Disable 0x1 = Enable
13	SPEED_SEL_LSB	R/W	0x0	Speed selection bits LSB[13] and MSB[6] are used to control the data rate of the ethernet link when auto-negotiation is disabled. 0x0 = 10Mbps 0x1 = 100Mbps 0x2 = 1000Mbps 0x3 = Reserved
12	AUTONEG_EN	R/W	0x1	Controls autonegotiation feature 0x0 = Autonegotiation off 0x1 = Autonegotiation on
11	PWD_DWN	R	0x0	Controls IEEE power down feature 0x0 = Normal Mode 0x1 = IEEE power down mode
10	ISOLATE	R/W	0x0	Isolate MAC interface pins. 0x0 = Normal mode 0x1 = MAC Isolate mode enabled
9	RSTRT_AUTONEG	RH/WtoP	0x0	Restart auto-negotiation 0x0 = Normal mode 0x1 = Restart autonegotiation
8	DUPLEX_EN	R/W	0x1	Controls Half and Full duplex mode of the ethernet link 0x0 = Half Duplex mode 0x1 = Full Duplex mode
7	COL_TST	R/W	0x0	Controls Collision Signal Test 0x0 = Disable Collision Signal Test 0x1 = Enable Collision Signal Test
6	SPEED_SEL_MSB	R	0x1	Controls data rate of ethernet link when autonegotiation is disabled. See bit 13 description for morw information.
5-0	RESERVED	R	0x0	Reserved

7.6.1.2 BMSR Register (Offset = 0x1) [Reset = 0x7949]

BMSR is shown in Table 7-13.

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IEEE defined register to show status of PHY

Table 7-13 BMSR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0x0	Reserved
14	100M_FDUP	R	0x1	100Base-TX full duplex 0x0 = PHY not able to perform full duplex 100Base-X 0x1 = PHY able to perform full duplex 100Base-X
13	100M_HDUP	R	0x1	100Base-TX halfduplex 0x0 = PHY not able to perform half duplex 100Base-X 0x1 = PHY able to perform half duplex 100Base-X
12	10M_FDUP	R	0x1	10Base-Te full duplex 0x0 = PHY not able to operate at 10Mbps in full duplex 0x1 = PHY able to operate at 10Mbps in full duplex
11	10M_HDUP	R	0x1	10Base-Te half duplex 0x0 = PHY not able to operate at 10Mbps in half duplex 0x1 = PHY able to operate at 10Mbps in half duplex
10	RESERVED	R	0x0	Reserved
9	RESERVED	R	0x0	Reserved
8	EXT_STS	R	0x1	Extended status for 1000Base T abilities in register 15 0x1 = Extended status information in register 0x0F
7	RESERVED	R	0x0	Reserved
6	MF_PREAMBLE_SUP	R	0x1	Ability to accept management frames with preamble suppressed. For the Preamble suppression mode - a minimum of 1 preamble is required for DP83561-SP PHY 0x0 = PHY will not accept management frames with preamble suppressed 0x1 = PHY will accept management frames with preamble suppressed
5	AUTONEG_COMP	R	0x0	Status of Autonegotiation 0x0 = Auto Negotiation process not completed 0x1 = Auto Negotiation process completed
4	REMOTE_FAULT	RC	0x0	Remote fault detection 0x0 = No remote fault condition detected 0x1 = Remote fault condition detected
3	AUTONEG_ABL	R	0x1	Autonegotiation ability 0x0 = PHY is not able to perform Auto-Negotiation 0x1 = PHY is able to perform Auto-Negotiation
2	LINK_STS1	R	0x0	Link Status This is latch low and needs to be read twice for valid link up 0x0 = Link down 0x1 = Link up
1	JABBER_DTCT	RC	0x0	Jabber detected 0x0 = No jabber detected 0x1 = Jabber detected
0	EXT_CAPBLTY	R	0x1	Extended register capabilities 0x0 = Basic register set capabilities 0x1 = Extended register set capabilities

7.6.1.3 PHYIDR1 Register (Offset = 0x2) [Reset = 0x2000]

PHYIDR1 is shown in Table 7-14.

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The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83561SP. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. Texas Instruments' IEEE assigned OUI is 080028h.

Table 7-14 PHYIDR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	OUI_MSB	R	0x2000	OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are stored in bits 15 to 0 of this register respectively. Bit numbering for OUI goes from 1 (MSB) to 24(LSB). The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2).

7.6.1.4 PHYIDR2 Register (Offset = 0x3) [Reset = 0xA1A4]

PHYIDR2 is shown in Table 7-15.

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Table 7-15 PHYIDR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	OUI_LSB	R	0x28	OUI Least Significant Bits: Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of this register respectively.
9-4	MODEL_NUM	R	0x1A	Model number: The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9).
3-0	REVISION_NUM	R	0x4	Revision number: Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant bit to bit 3). This field will be incremented for all major device changes.

7.6.1.5 ANAR Register (Offset = 0x4) [Reset = 0x1E1]

ANAR is shown in Table 7-16.

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This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a renegotiation. This will ensure that the new values are properly used in the Auto-Negotiation.

Table 7-16 ANAR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	NEXT_PAGE_1_ADV	R/W	0x0	Next Page Advertisement 0x0 = Do not advertise desire to send additional SW next pages 0x1 = Advertise desire to send additional SW next pages
14	RESERVED	R	0x0	Reserved
13	REMOTE_FAULT_ADV	R/W	0x0	Remote Fault Advertisement 0x0 = Do not advertise remote fault event detection 0x1 = Advertise remote fault event detection
12	ANAR_BIT12	R/W	0x0
11	ASYMMETRIC_PAUSE_ADV	R/W	0x0	1b = Advertise asymmetric pause ability 0b = Do not advertise asymmetric pause ability
10	PAUSE_ADV	R/W	0x0	0x0 = Do not advertise pause ability 0x1 = Advertise pause ability
9	G_100BT_4_ADV	R/W	0x0	100BT-4 is not supported
8	G_100BTX_FD_ADV	R/W	0x1	100Base-TX Full Duplex. Default depends on strap, non strap default '1'. 0x0 = Do not advertise 100Base-TX Full Duplex ability 0x1 = Advertise 100Base-TX Full Duplex ability
7	G_100BTX_HD_ADV	R/W	0x1	100Base-TX Half Duplex. Default depends on strap, non strap default '1'. 0x0 = Do not advertise 100Base-TX Half Duplex ability 0x1 = Advertise 100Base-TX Half Duplex ability
6	G_10BT_FD_ADV	R/W	0x1	Default depends on strap, non strap default '1' 0x0 = Do not advertise 10Base-T Full Duplex ability 0x1 = Advertise 10Base-T Full Duplex ability
5	G_10BT_HD_ADV	R/W	0x1	Default depends on strap, non strap default '1' 0x0 = Do not advertise 10Base-T Half Duplex ability 0x1 = Advertise 10Base-T Half Duplex ability
4-0	SELECTOR_FIELD_ADV	R/W	0x1	Technology selector field (802.3 == 00001)

7.6.1.6 ALNPAR Register (Offset = 0x5) [Reset = 0x0]

ALNPAR is shown in Table 7-17.

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This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful Auto-Negotiation if Next pages are supported.

Table 7-17 ALNPAR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	NEXT_PAGE_1_LP	R	0x0	0x0 = Link Partner does not advertise desire to send additional SW next pages 0x1 = Link Partner advertises desire to send additional SW next pages
14	ACKNOWLEDGE_1_LP	R	0x0	0x0 = Link Partner does not acknowledge reception of link partner's link code word 0x1 = Link Partner acknowledges reception of link partner's link code word
13	REMOTE_FAULT_LP	R	0x0	0x0 = Link Partner does not advertise remote fault event detection 0x1 = Link Partner advertises remote fault event detection
12	RESERVED	R	0x0	Reserved
11	ASYMMETRIC_PAUSE_LP	R	0x0	0x0 = Link Partner does not advertise asymmetric pause ability 0x1 = Link Partner advertises asymmetric pause ability
10	PAUSE_LP	R	0x0	0x0 = Link Partner does not advertise pause ability 0x1 = Link Partner advertises pause ability
9	G_100BT4_LP	R	0x0	0x0 = Link Partner does not advertise 100Base-T4 ability 0x1 = Link Partner advertises 100Base-T4 ability
8	G_100BTX_FD_LP	R	0x0	0x0 = Link Partner does not advertise 100Base-TX Full Duplex ability 0x1 = Link Partner advertises 100Base-TX Full Duplex ability
7	G_100BTX_HD_LP	R	0x0	0x0 = Link Partner does not advertise 100Base-TX Half Duplex ability 0x1 = Link Partner advertises 100Base-TX Half Duplex ability
6	G_10BT_FD_LP	R	0x0	0x0 = Link Partner does not advertise 10Base-T Full Duplex ability 0x1 = Link Partner advertises 10Base-T Full Duplex ability
5	G_10BT_HD_LP	R	0x0	0x0 = Link Partner does not advertise 10Base-T Half Duplex ability 0x1 = Link Partner advertises 10Base-T Half Duplex ability
4-0	SELECTOR_FIELD_LP	R	0x0	Technology selector field

7.6.1.7 ANER Register (Offset = 0x6) [Reset = 0x64]

ANER is shown in Table 7-18.

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This register contains additional Local Device and Link Partner status information.

Table 7-18 ANER Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	RESERVED	R	0x0	Reserved
6	RX_NEXT_PAGE_LOC_ABLE	R	0x1	0x0 = Received Next Page storage location is not specified by bit 6.5 0x1 = Received Next Page storage location is specified by bit 6.5
5	RX_NEXT_PAGE_STOR_LOC	R	0x1	0x0 = Link Partner Next Pages are stored in register 5 0x1 = Link Partner Next Pages are stored in register 8
4	PRLL_TDCT_FAULE	RC	0x0	THIS STATUS IS LH (Latched-High) 0x0 = A fault has not been detected during the parallel detection process 0x1 = A fault has been detected during the parallel detection process
3	LP_NP_ABLE	R	0x0	0x0 = Link partner is not able to exchange next pages 0x1 = Link partner is able to exchange next pages
2	LOCAL_NP_ABLE	R	0x1	0x0 = Local device is not able to exchange next pages 0x1 = Local device is able to exchange next pages
1	PAGE_RECEIVED_1	RC	0x0	THIS STATUS IS LH (Latched-High) 0x0 = A new page has not been received 0x1 = A new page has been received
0	LP_AUTONEG_ABLE	R	0x0	0x0 = Link partner is not Auto-Negotiation able 0x1 = Link partner is Auto-Negotiation able

7.6.1.8 ANNPTR Register (Offset = 0x7) [Reset = 0x2001]

ANNPTR is shown in Table 7-19.

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This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

Table 7-19 ANNPTR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	NEXT_PAGE_2_ADV	R/W	0x0	0x0 = Do not advertise desire to send additional next pages 0x1 = Advertise desire to send additional next pages
14	RESERVED	R	0x0	Reserved
13	MESSAGE_PAGE	R/W	0x1	0x0 = Current page is an unformatted page 0x1 = Current page is a message page
12	ACKNOWLEDGE2	R/W	0x0	0x0 = Do not set the ACK2 bit 0x1 = Set the ACK2 bit
11	TOGGLE	R	0x0	Toggles every page. Initial value is !4.11
10-0	MESSAGE_UNFORMATTED	R/W	0x1	Contents of the message/unformatted page

7.6.1.9 ANLNPTR Register (Offset = 0x8) [Reset = 0x2001]

ANLNPTR is shown in Table 7-20.

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This register contains the next page information sent by the Link Partner during Auto-Negotiation.

Table 7-20 ANLNPTR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	NEXT_PAGE_2_LP	R	0x0	0x0 = Link partner does not advertise desire to send additional next pages 0x1 = Link partner advertises desire to send additional next pages
14	ACKNOWLEDGE_2_LP	R	0x0	0x0 = Link partner does not acknowledge reception of link code work 0x1 = Link partner acknowledges reception of link code word
13	MESSAGE_PAGE_LP	R	0x1	0x0 = Received page is an unformatted page 0x1 = Received page is a message page
12	ACKNOWLEDGE2_LP	R	0x0	0x0 = Link partner does not set the ACK2 bit 0x1 = Link partner sets the ACK2 bit
11	TOGGLE_LP	R	0x0	Toggles every page. Initial value is !5.11
10-0	MESSAGE_UNFORMATTED_LP	R	0x1	Contents of the message/unformatted page

7.6.1.10 GEN_CFG1 Register (Offset = 0x9) [Reset = 0x300]

GEN_CFG1 is shown in Table 7-21.

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Table 7-21 GEN_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	TEST_MODE	R/W	0x0	0x0 = Normal Mode 0x1 = Test Mode 1 - Transmit Waveform Test 0x2 = Test Mode 2 - Transmit Jitter Test (Master Mode) 0x3 = Test Mode 3 - Transmit Jitter Test (Slave Mode) 0x4 = Test Mode 4 - Transmit Distortion Test 0x5 = Test Mode 5 - Scrambled MLT3 Idles 0x6 = Test Mode 6 - Repetitive 0001 sequence 0x7 = Test Mode 7 - Repetitive {Pulse, 63 zeros}
12	MASTER_SLAVE_MAN_CFG_EN	R/W	0x0	1 = Enable manual Master/Slave configuration 0 = Do not enable manual Master/Slave configuration
11	MASTER_SLAVE_MAN_CFG_VAL	R/W	0x0	1 = Manual configure as Master 0 = Manual configure as Slave
10	PORT_TYPE	R/W	0x0	1 = Multi-port device 0 = Single-port device
9	G_1000BT_FD_ADV	R/W	0x1	Default depends on strap 0x0 = Do not advertise 1000Base-T Full Duplex ability 0x1 = Advertise 1000Base-T Full Duplex ability
8	G_1000BT_HD_ADV	R/W	0x1	Default depends on strap 0x0 = Do not advertise 1000Base-T Half Duplex ability 0x1 = Advertise 1000Base-T Half Duplex ability
7	TDR_AUTO_RUN	R/W	0x0	TDR Auto Run at link down: 0x0 = Disable automatic execution of TDR 0x1 = Enable execution of TDR procedure after link down event
6-0	RESERVED	R	0x0	Reserved

7.6.1.11 GEN_STATUS1 Register (Offset = 0xA) [Reset = 0x0]

GEN_STATUS1 is shown in Table 7-22.

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Table 7-22 GEN_STATUS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	MS_CONFIG_FAULT	RC	0x0	1 = Master/Slave configuration fault detected 0 = No Master/Slave configuration fault detected THIS STATUS IS LH (Latched-High)
14	MS_CONFIG_RES	R	0x0	1 = Local PHY configuration resolved to Master 0 = Local PHY configuration resolved to Slave
13	LOC_RCVR_STATUS_1	R	0x0	1 = Local receiver is OK 0 = Local receiver is not OK
12	REM_RCVR_STATUS	R	0x0	1 = Remote receiver is OK 0 = Remote receiver is not OK
11	LP_1000BT_FD_ABILITY	R	0x0	1 = Link partner supports 1000Base-T Full Duplex ability 0 = Link partner does not support 1000Base-T Full Duplex ability
10	LP_1000BT_HD_ABILITY	R	0x0	1 = Link partner supports 1000Base-T Half Duplex ability 0 = Link partner does not support 1000Base-T Half Duplex ability
9-8	RESERVED	R	0x0	Reserved
7-0	IDLE_ERR_COUNT	R	0x0	1000Base-T Idle Error Counter

7.6.1.12 REGCR Register (Offset = 0xD) [Reset = 0x0]

REGCR is shown in Table 7-23.

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This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the device address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate MMD. REGCR also contains selection bits for auto increment of the data register. This register contains the device address to be written to access the extended registers. Write 0x1F into bits 4:0 of this register. REGCR also contains selection bits (15:14) for the address auto-increment mode of ADDAR.

Table 7-23 REGCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	G_FUNCTION	R/W	0x0	00 = Address 01 = Data, no post increment 10 = Data, post increment on read and write 11 = Data, post increment on write only
13-5	RESERVED	R	0x0	Reserved
4-0	DEVAD	R/W	0x0	Device Address

7.6.1.13 ADDAR Register (Offset = 0xE) [Reset = 0x0]

ADDAR is shown in Table 7-24.

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This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register (0x000D) to provide the access by indirect read/write mechanism to the extended register set.

Table 7-24 ADDAR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	ADDR_DATA	R/W	0x0	If register 13.15:14 = 00, holds the MMD DEVAD's address register, otherwise holds the MMD DEVAD's data register

7.6.1.14 1KSCR Register (Offset = 0xF) [Reset = 0xF000]

1KSCR is shown in Table 7-25.

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Table 7-25 1KSCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	G_1000BX_FD	R	0x1	1 = PHY supports 1000Base-X Full Duplex capability 0 = PHY does not support 1000Base-X Full Duplex capability
14	G_1000BX_HD	R	0x1	1 = PHY supports 1000Base-X Half Duplex capability 0 = PHY does not support 1000Base-X Half Duplex capability
13	G_1000BT_FD	R	0x1	1 = PHY supports 1000Base-T Full Duplex capability 0 = PHY does not support 1000Base-T Full Duplex capability
12	G_1000BT_HD	R	0x1	1 = PHY supports 1000Base-T Half Duplex capability 0 = PHY does not support 1000Base-T Half Duplex capability
11-0	RESERVED	R	0x0	Reserved

7.6.1.15 PHY_CONTROL Register (Offset = 0x10) [Reset = 0x5048]

PHY_CONTROL is shown in Table 7-26.

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Table 7-26 PHY_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	TX_FIFO_DEPTH	R/W	0x1	FIFO is enabled only in the following modes: 1000BaseT + GMII 0x0 = 3 bytes/nibbles (1000Mbps/Other Speeds) 0x1 = 4 bytes/nibbles (1000Mbps/Other Speeds) 0x2 = 6 bytes/nibbles (1000Mbps/Other Speeds) 0x3 = 8 bytes/nibbles (1000Mbps/Other Speeds)
13-12	RX_FIFO_DEPTH	R/W	0x1	FIFO is enabled only when SGMII is used 0x0 = 3 bytes/nibbles (1000Mbps/Other Speeds) 0x1 = 4 bytes/nibbles (1000Mbps/Other Speeds) 0x2 = 6 bytes/nibbles (1000Mbps/Other Speeds) 0x3 = 8 bytes/nibbles (1000Mbps/Other Speeds)
11	RESERVED	R	0x0	Reserved
10	FORCE_LINK_GOOD	R/W	0x0	0x0 = Do Normal operation 0x1 = Force Link OK if speed is 1G
9-8	POWER_SAVE_MODE	R/W	0x0	0x0 = Normal mode 0x1 = Reserved 0x2 = Active Sleep mode 0x3 = Passive Sleep mode
7	RESERVED	R	0x0	Reserved
6-5	MDI_CROSSOVER_MODE	R/W	0x2	Default depends on strap 0x0 = Manual MDI configuration 0x1 = Manual MDI-X configuration 0xA = Enable automatic crossover 0xB = Enable automatic crossover
4	DISABLE_CLK_125	R/W	0x0	0x0 = Enable CLK125 0x1 = Disable CLK125
3	TEST_CLKOUT_SEL	R/W	0x1	0x0 = Test clock is output through GMII_RX_CLK pin 0x1 = Test clock is output through CLK_125_OUT pin
2	RESERVED	R	0x0	Reserved
1	LINE_DRIVER_INV_EN	R/W	0x0	This bit is not applicable in Mirror mode 0x0 = Do not Invert LD transmission 0x1 = Invert LD transmission
0	DISABLE_JABBER	R/W	0x0	0x0 = Enable Jabber function 0x1 = Disable Jabber function

7.6.1.16 PHY_STATUS Register (Offset = 0x11) [Reset = 0x0]

PHY_STATUS is shown in Table 7-27.

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Table 7-27 PHY_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	SPEED_SEL	R	0x0	00 = 10Mbps 01 = 100Mbps 10 = 1000Mbps 11 = Reserved
13	DUPLEX_MODE_ENV	R	0x0	1 = Full duplex 0 = Half duplex
12	PAGE_RECEIVED_2	RC	0x0	1 = Page received 0 = Page not received THIS BIT IS LH (Latched-High)
11	SPEED_DUPLEX_RESOLVED	R	0x0	1 = Auto-Negotiation completed or disabled 0 = Auto-Negotiation enabled and not completed
10	LINK_STATUS_2	R	0x0	1 = Link is up 0 = Link is down
9	MDI_X_MODE_CD_1	R	0x0	1 = MDI-X 0 = MDI
8	MDI_X_MODE_AB_1	R	0x0	1 = MDI-X 0 = MDI
7	SPEED_OPT_STATUS	R	0x0	1 = Auto-Negotiation is currently being performed with Speed Optimization masking 1000BaseT abilities (Valid only during Auto-Negotiation) 0 = Auto-Negotiation is currently being performed without Speed Optimization
6	SLEEP_MODE	R	0x0	1 = Sleep 0 = Active
5-2	WIRE_CROSS	R	0x0	Indicates channels [D,C,B,A] polarity in 1000BT link 1 = Channel polarity is reversed 0 = Channel polarity is normal
1	DATA_POLARITY	R	0x0	1 = 10BT is in normal polarity 0 = 10BT is in reversed polarity
0	JABBER_DTCT_2	R	0x0	1 = Jabber 0 = No Jabber

7.6.1.17 INTERRUPT_MASK Register (Offset = 0x12) [Reset = 0x0]

INTERRUPT_MASK is shown in Table 7-28.

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This register implements the Interrupt PHY Specific Control register. The individual interrupt events must be enabled by setting bits in the MII Interrupt Control Register (MICR). If the corresponding enable bit in the register is set, an interrupt is generated if the event occurs.

Table 7-28 INTERRUPT_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
15	AUTONEG_ERR_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
14	SPEED_CHNG_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
13	DUPLEX_MODE_CHNG_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
12	PAGE_RECEIVED_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
11	AUTONEG_COMP_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
10	LINK_STATUS_CHNG_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
9	EEE_ERR_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
8	FALSE_CARRIER_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
7	ADC_FIFO_OVF_UNF_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
6	MDI_CROSSOVER_CHNG_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
5	SPEED_OPT_EVENT_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
4	SLEEP_MODE_CHNG_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
3	WOL_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
2	XGMII_ERR_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
1	POLARITY_CHNG_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt
0	JABBER_INT_EN	R/W	0x0	1 = Enable interrupt 0 = Disable interrupt

7.6.1.18 INTERRUPT_STATUS Register (Offset = 0x13) [Reset = 0x0]

INTERRUPT_STATUS is shown in Table 7-29.

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This register contains event status for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. The status indications in this register will be set even if the interrupt is not enabled.

Table 7-29 INTERRUPT_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15	AUTONEG_ERR	RC	0x0	1 = Auto-Negotiation error has occurred 0 = Auto-Negotiation error has not occurred THIS BIT IS LH (Latched-High)
14	SPEED_CHNG	RC	0x0	1 = Link speed has changed 0 = Link speed has not changed THIS BIT IS LH (Latched-High)
13	DUPLEX_MODE_CHNG	RC	0x0	1 = Duplex mode has changed 0 = Duplex mode has not changed THIS BIT IS LH (Latched-High)
12	PAGE_RECEIVED	RC	0x0	1 = Page has been received 0 = Page has not been received THIS BIT IS LH (Latched-High)
11	AUTONEG_COMP	RC	0x0	1 = Auto-Negotiation has completed 0 = Auto-Negotiation has not completed THIS BIT IS LH (Latched-High)
10	LINK_STATUS_CHNG	RC	0x0	1 = Link status has changed 0 = Link status has not changed THIS BIT IS LH (Latched-High)
9	EEE_ERR_STATUS	R	0x0	1 = EEE error has been detected
8	FALSE_CARRIER	RC	0x0	1 = Enable interrupt 0 = Disable interrupt THIS BIT IS LH (Latched-High)
7	ADC_FIFO_OVF_UNF	RC	0x0	1 = Overflow / underflow has been detected in one of ADC's FIFOs THIS BIT IS LH (Latched-High)
6	MDI_CROSSOVER_CHNG	RC	0x0	1 = MDI crossover has changed 0 = MDI crossover has not changed THIS BIT IS LH (Latched-High)
5	SPEED_OPT_EVENT	RC	0x0	1 = MDI crossover has changed 0 = MDI crossover has not changed THIS BIT IS LH (Latched-High)
4	SLEEP_MODE_CHNG	RC	0x0	1 = Sleep mode has changed 0 = Sleep mode has not changed THIS BIT IS LH (Latched-High)
3	WOL_STATUS	R	0x0	1 = WoL (or pattern) packet has been received
2	XGMII_ERR_STATUS	R	0x0	1 = Overflow / underflow has been detected in one of GMII / RGMII buffers NOTE: this indication have issue, recommend to not put on DS, unless proven otherwise on the lab, CDDS #475
1	POLARITY_CHNG	R	0x0	1 = Data polarity has changed 0 = Data polarity has not changed THIS BIT IS LH (Latched-High)
0	JABBER	RC	0x0	1 = Jabber detected 0 = Jabber not detected THIS BIT IS LH (Latched-High)

7.6.1.19 GEN_CFG2 Register (Offset = 0x14) [Reset = 0x2947]

GEN_CFG2 is shown in Table 7-30.

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Table 7-30 GEN_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PD_DETECT_EN	RH/WtoP	0x0	0x0 = Disable PD detection 0x1 = Enable PD (Powered Device) detection
14	RESERVED	R	0x0	Reserved
13	INTERRUPT_POLARITY	R/W	0x1	0x0 = Interrupt pin is active high 0x1 = Interrupt pin is active low
12	RESERVED	R	0x0	Reserved
11-10	SPEED_OPT_ATTEMPT_CNT	R/W	0x2	Selects the number of 1G link establishment attempt failures prior to performing Speed Optimization: 0x0 = 1 attempt 0x1 = 2 attempts 0x2 = 4 attempts 0x3 = 8 attempts
9	SPEED_OPT_EN	R/W	0x0	0x0 = Disable Speed Optimization 0x1 = Enable Speed Optimization
8	SPEED_OPT_ENHANCED_EN	R/W	0x1	In enhanced mode, speed is optimized if energy is not detected in channels C and D 0x0 = Disable Speed Optimization enhanced mode 0x1 = Enable Speed Optimization enhanced mode
7	RESERVED	R	0x0	Reserved
6	SPEED_OPT_10M_EN	R/W	0x1	0x0 = Disable speed optimization to 10M 0x1 = Enable speed optimization to 10M (If link establishments of 1G and 100M fail)
5-4	MII_CLK_CFG	R/W	0x0	Selects frequency of GMII_TX_CLK in 1G mode: 0x0 = 2.5Mhz 0x1 = 25Mhz 0x2 = Disabled 0x3 = Disabled
3	COL_FD_EN	R/W	0x0	0x0 = Disable COL indication in full duplex mode 0x1 = Enable COL indication in full duplex mode
2	LEGACY_CODING_TXMODE_EN	R/W	0x1	0x0 = Disable automatic selection of Legacy scrambler mode in 1G, Master mode 0x1 = Enable automatic selection of Legacy scrambler mode in 1G, Master mode
1	MASTER_SEMI_CROSS_EN	R/W	0x1	0x0 = Disable semi-cross mode in 1G Master mode 0x1 = Enable semi-cross mode in 1G Master mode
0	SLAVE_SEMI_CROSS_EN	R/W	0x1	0x0 = Disable semi-cross mode in 1G Slave mode 0x1 = Enable semi-cross mode in 1G Slave mode

7.6.1.20 RX_ERR_CNT Register (Offset = 0x15) [Reset = 0x0]

RX_ERR_CNT is shown in Table 7-31.

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Table 7-31 RX_ERR_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RX_ERROR_COUNT	R/W1C	0x0	Receive Error Counter

7.6.1.21 BIST_CONTROL Register (Offset = 0x16) [Reset = 0x0]

BIST_CONTROL is shown in Table 7-32.

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This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact loopback point in the signal chain is also done in this register.

Table 7-32 BIST_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	PACKET_GEN_EN_3:0	R/W	0x0	These bits along controls PRBS generator. Other values are not applicable. 0x0 = Disable PRBS 0xF = Enable Continuous PRBS
11-10	RESERVED	R	0x0	Reserved
9	RESERVED	R	0x0	Reserved
8	RESERVED	R	0x0	Reserved
7	REV_LOOP_RX_DATA_CTRL	R/W	0x0	Reverse Loopback Receive Data Control: This bit may only be set in Reverse Loopback mode 0x0 = Suppress RX packets to MAC in reverse loop 0x1 = Send RX packets to MAC in reverse loop
6	MII_LOOP_TX_DATA_CTRL	R/W	0x0	MII Loopback Transmit Data Control: This bit may only be set in MII Loopback mode 0x0 = Suppress data to MDI in MII loop 0x1 = Transmit data to MDI in MII loop
5-2	LOOP_TX_DATA_MIX	R/W	0x0	Loopback Mode Select: PCS loopback must be disabled (Bits[1:0] = 00) 0x0 = No Loopback 0x1 = Digital Loopback 0x2 = Analog Loopback 0x4 = External Loopback 0x8 = Reverse Loopback
1-0	LOOPBACK_MODE	R/W	0x0	PCS Loopback Select When configured in 1000Base-T x1b = Loop before 1000Base-T signal processing. When configured in 100Base-TX 0x0 = See bits [5:2] 01b = Loop before scrambler 10b = Loop after scrambler, before MLT3 encoder 11b = Loop after MLT3 encoder

7.6.1.22 GEN_STATUS2 Register (Offset = 0x17) [Reset = 0x40]

GEN_STATUS2 is shown in Table 7-33.

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Table 7-33 GEN_STATUS2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	PD_PASS	RC	0x0	1b = PD (Powered Device) has been successfully detected 0b = PD has not been detected
14	PD_PULSE_DET_ZERO	RC	0x0	1b = PD detection mechanism has received no signal 0b = PD detection mechanism has received signal
13	PD_FAIL_WD	RC	0x0	1b = PD detection mechanism watchdog has expired 0b = PD detection mechanism watchdog has not expired
12	PD_FAIL_NON_PD	RC	0x0	1b = PD detection mechanism has detected a non-powered device 0b = PD detection mechanism has not detected a non-powered device
11	PRBS_LOCK	R	0x0	1b = PRBS checker is locked sync) on received byte stream 0b = PRBS checker is not locked
10	PRBS_SYNC_LOSS	R	0x0	1b = PRBS checker has lost sync 0b = PRBS checker has not lost sync LH - clear on read register
9	PKT_GEN_BUSY	R	0x0	1b = Packet generator is in process 0b = Packet generator is not in process
8	SCR_MODE_MASTER_1G	R	0x0	1b = 1G PCS (master) is in legacy encoding mode 0b = 1G PCS (master) is in normal encoding mode
7	SCR_MODE_SLAVE_1G	R	0x0	1b = 1G PCS (slave) is in legacy encoding mode 0b = 1G PCS (slave) is in normal encoding mode
6	CORE_PWR_MODE	R	0x1	1b = Core is in normal power mode 0b = Core is powered down or in sleep mode
5-0	RESERVED	R	0x0	Reserved

7.6.1.23 LEDS_CFG1 Register (Offset = 0x18) [Reset = 0x6150]

LEDS_CFG1 is shown in Table 7-34.

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Table 7-34 LEDS_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	LED_GPIO_SEL	R/W	0x6	Source of GPIO LED, same as bits 3:0
11-8	LED_2_SEL	R/W	0x1	Source of LED_2 (LED 2) , same as bits 3:0
7-4	LED_1_SEL	R/W	0x5	Source of LED_1 (LED 1) , same as bits 3:0
3-0	LED_0_SEL	R/W	0x0	Source of LED_0 (LED 0) 0x0 = link OK 0x1 = RX/TX activity 0x2 = TX activity 0x3 = RX activity 0x4 = collision detected 0x5 = 1000BT link is up 0x6 = 100 BTX link is up 0x7 = 10BT link is up 0x8 = 10/100BT link is up 0x9 = 100/1000BT link is up 0xA = full duplex 0xB = link OK + blink on TX/RX activity 0xC = NA 0xD = RX_ER or TX_ER 0xE = RX_ER

7.6.1.24 LEDS_CFG2 Register (Offset = 0x19) [Reset = 0x4444]

LEDS_CFG2 is shown in Table 7-35.

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Table 7-35 LEDS_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0x0	Reserved
14	LED_GPIO_POLARITY	R/W	0x1	GPIO LED polarity: Default depends on strap, non strap default Active High 0x0 = Active low 0x1 = Active high
13	LED_GPIO_DRV_VAL	R/W	0x0	If bit #12 is set, this is the value of GPIO LED
12	LED_GPIO_DRV_EN	R/W	0x0	Force value to LED_GPIO as per bit #13 0x0 = LED_GPIO is in normal operation mode 0x1 = Force the value of LED_GPIO
11	RESERVED	R	0x0	Reserved
10	LED_2_POLARITY	R/W	0x1	LED_2 polarity. Default depends on strap, non strap default Active High 0x0 = Active low 0x1 = Active high
9	LED_2_DRV_VAL	R/W	0x0	If bit #8 is set, this is the value of LED_2
8	LED_2_DRV_EN	R/W	0x0	Force value to LED_GPIO as per bit #9 0x0 = LED_2 is in normal operation mode 0x1 = Drive the value of LED_2
7	RESERVED	R	0x0	Reserved
6	LED_1_POLARITY	R/W	0x1	LED_1 polarity: Default depends on strap, non strap default Active High 0x0 = Active low 0x1 = Active high
5	LED_1_DRV_VAL	R/W	0x0	If bit #4 is set, this is the value of LED_1
4	LED_1_DRV_EN	R/W	0x0	Force value to LED_GPIO as per bit #5 0x0 = LED_1 is in normal operation mode 0x1 = Drive the value of LED_1
3	RESERVED	R	0x0	Reserved
2	LED_0_POLARITY	R/W	0x1	LED_0 polarity: Default depends on strap, non strap default Active High 0x0 = Active low 0x1 = Active high
1	LED_0_DRV_VAL	R/W	0x0	If bit #1 is set, this is the value of LED_0
0	LED_0_DRV_EN	R/W	0x0	Force value to LED_GPIO as per bit #1 0x0 = LED_0 is in normal operation mode 0x1 = Drive the value of LED_0

7.6.1.25 LEDS_CFG3 Register (Offset = 0x1A) [Reset = 0x2]

LEDS_CFG3 is shown in Table 7-36.

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Table 7-36 LEDS_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0x0	Reserved
2	LEDS_BYPASS_STRETCHING	R/W	0x0	0b = Normal Operation 1b = Bypass LEDs stretching
1-0	LEDS_BLINK_RATE	R/W	0x2	00b = 20Hz (50mSec) 01b = 10Hz (100mSec) 10b = 5Hz (200mSec) 11b = 2Hz (500mSec)

7.6.1.26 GEN_CFG4 Register (Offset = 0x1E) [Reset = 0x2]

GEN_CFG4 is shown in Table 7-37.

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Table 7-37 GEN_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0x0	Reserved
14	CFG_FAST_ANEG_EN	R/W	0x0	Enable Fast ANEG mode
13-12	CFG_FAST_ANEG_SEL_VAL	R/W	0x0	when Fast ANEG mode enabled, value will select short timer duration 0x0 will be the shortest timers config and 0x2 the longest
11	CFG_ANEG_ADV_FD_EN	R/W	0x0	this but enables to declare FD also in parallel detect link, the IEEE define on parallel detect to always declare HD, this bit allows also to declare FD in this scenario
10	RESTART_STATUS_BITS_EN	R/W	0x0	reset enable 1b = clear all the phy status bits (part of register 0x11) 0b = do not clear the status bit
9	CFG_ROBUST_AMDIX_EN	R/W	0x0	Enable Robust Auto MDI/MDIX resolution
8	CFG_FAST_AMDIX_EN	R/W	0x0	Enabe Fast Auto MDI-X mode
7	INT_OE	R/W	0x0	Interrupt Output Enable: 1b = INTN/PWDNN Pad is an Interrupt Output 0b = INTN/PWDNN Pad in an Power Down Input
6	FORCE_INTERRUPT	R/W	0x0	1b = Assert interrupt pin 0b = Normal interrupt mode
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	FORCE_1G_AUTONEG_EN	R/W	0x0	1b = Invoke Auto-Negotiation with only 1G advertised when manual speed in register 0 is 1G 0b = Do not invoke Auto-Negotiation when manual speed in register 0 is 1G
2	TDR_FAIL	R	0x0
1	TDR_DONE	R	0x1
0	TDR_START	RH/WtoP	0x0	1b = Start TDR 0b = TDR Completed

7.6.1.27 GEN_CTRL Register (Offset = 0x1F) [Reset = 0x0]

GEN_CTRL is shown in Table 7-38.

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Table 7-38 GEN_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	SW_RESET	RH/WtoP	0x0	Software Reset This will reset the PHY and return registers to their default values. Registers controlled via strap pins will return back to their last strapped values. 0x0 = Normal mode 0x1 = Reset PHY
14	SW_RESTART	RH/WtoP	0x0	Soft Restart Restarts the PHY without affecting registers. 0x0 = Normal Operation 0x1 = Software Reset
13	RESERVED	R	0x0	Reserved
12-7	RESERVED	R	0x0	Reserved
6-0	RESERVED	R	0x0	Reserved

7.6.1.28 ANALOG_TEST_CTRL Register (Offset = 0x25) [Reset = 0x480]

ANALOG_TEST_CTRL is shown in Table 7-39.

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Table 7-39 ANALOG_TEST_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0x0	Reserved
11-10	TM7_PULSE_SEL	R/W	0x1	Selects pulse amplitude and polarity for Test Mode 7 (See register 0x9): 00b = +2 01b = -2 10b = +1 11b = -1
9	EXTND_TM7_100BT_MSB	R/W	0x0	MSB of configurable length for 100BT extended TM7 For 100BT Test Mode: repetitive sequence of "1" with configurable number of "0". Bits { 9,[3:0] } define the number of "0" to follow the "1", from 1 to 31. 0,0001 - 1,1111 : single "0" to 31 zeros. 0,0000 - clear the shiftreg.
8	EXTND_TM7_100BT_EN	R/W	0x0	Enable extended TM7 for 100M. NOTE1: bit 4 must be "0" for 100BT TestMode. NOTE2: 100BT testmode must be Clear before appling new Value. e.g, one need to write 0x0 before configuring new value. NOTE3: use FORCE100 for 100BT testing, via Reg0x0.
7-5	STIM_CH_SEL	R/W	0x4	Selects the channel(s) that outputs the test mode: If bit #7 is set, test mode is driven to all channels. If bit #7 is cleared, test mode is driven according to bits 6:5 - 00b = Channel A 01b = Channel B 10b = Channel C 11b = Channel D
4-0	ANALOG_TEST	R/W	0x0	Bit [4] enables 10BaseT test modes. Bits [3:0] select the 10BaseT test pattern, as follows: To operate extended TM7 for 100BT, bits 3:0 shall be configured as well - more details in bit #9 0000b = Single NLP 0001b = Single Pulse 1 0010b = Single Pulse 0 0011b = Repetitive 1 0100b = Repetitive 0 0101b = Preamble (repetitive "10") 0110b = Single 1 followed by TP_IDLE 0111b = Single 0 followed by TP_IDLE 1000b = Repetitive "1001" sequence 1001b = Random 10Base-T data 1010b = TP_IDLE_00 1011b = TP_IDLE_01 1100b = TP_IDLE_10 1101b = TP_IDLE_11 0110b = Proprietary T.M for amplitude, RFT, DCD and template for FT on tester (1000) ---> need to write register 0 0x2000

7.6.1.29 GEN_CFG_ENH_AMIX Register (Offset = 0x2C) [Reset = 0x141F]

GEN_CFG_ENH_AMIX is shown in Table 7-40.

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Table 7-40 GEN_CFG_ENH_AMIX Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0x0	Reserved
13-9	CFG_FLD_WINDW_CNT	R/W	0xA	Counter to define the window to look for fast link down criteria, default 10 µs
8-4	CFG_FAST_AMDIX_VAL	R/W	0x1	Timer of the mdi/x switch countering force 100m fast amdix mode, very fast as it need only to allow far end to detect energy ~4ms in default
3-0	CFG_ROBUST_AMDIX_VAL	R/W	0xF	The value of the timer that switch mdi/x in robust mode, this should be long timer to allow far end to still do parallel detect with the IEEE ANEG timers... default ~0.5s

7.6.1.30 GEN_CFG_FLD Register (Offset = 0x2D) [Reset = 0x0]

GEN_CFG_FLD is shown in Table 7-41.

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Table 7-41 GEN_CFG_FLD Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CFG_FORCE_DROP_LINK_EN	R/W	0x0	Drop link (stop transmitting) when no signal is received
14	FLD_BYPASS_MAX_WAIT_TIMER	R/W	0x0	If set, MAX_WAIT_TIMER is skipped (and therefore link is dropped faster)
13	SLICER_OUT_STUCK	R	0x0	indicate slicer)out_stuck status
12-8	FLD_STATUS	R	0x0	Fast link down status LH - clear on read register
7-5	RESERVED	R	0x0	Reserved
4-0	CFG_FAST_LINK_DOWN_MODES	R/W	0x0	5 bits for different fast link down option (can all work simultaniously): bit [0] - energy lost bit [1] - mse bit [2] - mlt3 errors bit [3] - rx_err bit [4] - descrambler sync loss

7.6.1.31 GEN_CFG_FLD_THR Register (Offset = 0x2E) [Reset = 0x221]

GEN_CFG_FLD_THR is shown in Table 7-42.

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Table 7-42 GEN_CFG_FLD_THR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0x0	Reserved
10-8	ENERGY_WINDOW_LEN_FLD	R/W	0x2	window length in FLD energy lost mode for energy detection accumulator
7	RESERVED	R	0x0	Reserved
6-4	ENERGY_ON_FLD_THR	R/W	0x2	energy lost threshold for FLD energy lost mode. energy_detected indication will be asserted when energy detector accumulator exceeds this threshold.
3	RESERVED	R	0x0	Reserved
2-0	ENERGY_LOST_FLD_THR	R/W	0x1	energy lost threshold for FLD energy lost mode energy_lost indication will be asserted if energy detector accumulator falls below this threshold.

7.6.1.32 GEN_CFG3 Register (Offset = 0x31) [Reset = 0x0]

GEN_CFG3 is shown in Table 7-43.

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Table 7-43 GEN_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0x0	Reserved
14	RESERVED	R	0x0	Reserved
13	RESERVED	R	0x0	Reserved
12	RESERVED	R	0x0	Reserved
11-9	RESERVED	R	0x0	Reserved
8	RESERVED	R	0x0	Reserved
7	RESERVED	R	0x0	Reserved
6-5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	RESERVED	R	0x0	Reserved
1	RESERVED	R	0x0	Reserved
0	PORT_MIRRORING_MODE	R/W	0x0	Port mirroring mode: 0 - Disabled 1 - Enabled

7.6.1.33 RGMII_CTRL Register (Offset = 0x32) [Reset = 0xD0]

RGMII_CTRL is shown in Table 7-44.

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Table 7-44 RGMII_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0x0	Reserved
14	RESERVED	R	0x0	Reserved
13	RESERVED	R	0x0	Reserved
12	RESERVED	R	0x0	Reserved
11	RESERVED	R	0x0	Reserved
10	RESERVED	R	0x0	Reserved
9	RESERVED	R	0x0	Reserved
8	RESERVED	R	0x0	Reserved
7	RESERVED	R/W	0x1	unused, default value should remain unchanged.
6-5	RGMII_RX_HALF_FULL_THR	R/W	0x2	RGMII RX sync FIFO half full threshold 2 lsbs [1:0], msb [2] in reg 0x33 In the RX our default is recovered mode (can change in reg 0x0060 #4 below) In recovered mode we can reduce the threshold in from 2 to 1, this will save 8 ns in 1G, and 40/400 in 100/10M
4-3	RGMII_TX_HALF_FULL_THR	R/W	0x2	RGMII TX sync FIFO half full threshold 2 lsbs [1:0], - the msb is on reg 0x33 - [2]
2	SUPPRESS_TX_ERR_EN	R/W	0x0
1	RGMII_TX_CLK_DELAY	R/W	0x0	RGMII Transmit Clock Delay 0x0 = RGMII transmit clock is shifted with respect to transmit data. 0x1 = RGMII transmit clock is aligned with respect to transmit data.
0	RGMII_RX_CLK_DELAY	R/W	0x0	RGMII Receive Clock Delay 0x0 = RGMII receive clock is shifted with respect to receive data. 0x1 = RGMII transmit clock is aligned with respect to receive data.

7.6.1.34 RGMII_CTRL2 Register (Offset = 0x33) [Reset = 0x0]

RGMII_CTRL2 is shown in Table 7-45.

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Table 7-45 RGMII_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-5	RESERVED	R	0x0	Reserved
4	RGMII_AF_BYPASS_EN	R/W	0x0	RGMII Async FIFO Bypass Enable: 1 = Enable RGMII Async FIFO Bypass. 0 = Normal operation.
3	RGMII_AF_BYPASS_DLY_EN	R/W	0x0	RGMII Async FIFO Bypass Delay Enable: 1 = Delay RX_CLK when operating in 10/100 with RGMII. 0 = Normal operation
2	LOW_LATENCY_10_100_EN	R/W	0x0	Low Latency 10/100 Enable: 1 = Enable low latency in 10/100 operation. 0 = Normal operation.
1	RESERVED	R	0x0	Reserved
0	RESERVED	R	0x0	Reserved

7.6.1.35 PRBS_TX_CHK_CTRL Register (Offset = 0x39) [Reset = 0x0]

PRBS_TX_CHK_CTRL is shown in Table 7-46.

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Table 7-46 PRBS_TX_CHK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0x0	Reserved
14-7	PRBS_TX_CHK_ERR_CNT	R	0x0	Holds number of errored bytes that received by the PRBS TX checker. When TX PRBS Count Mode (see bit [1]) set to 0, count stops on 0xFF. Notes: Writing bit 7 generates a lock signal for the PRBS TX counters. Writing bit 8 generates a lock and clear signal for the PRBS TX counters
6	RESERVED	R	0x0	Reserved
5	PRBS_TX_CHK_SYNC_LOSS	R	0x0	1b = PRBS TX checker has lost sync 0b = PRBS TX checker has not lost sync This bit is LH
4	PRBS_TX_CHK_LOCK_STS	R	0x0	1b = PRBS TX checker is locked on received byte stream 0b = PRBS TX checker is not locked
3	RESERVED	R	0x0	Reserved
2	PRBS_TX_CHK_BYTE_CNT_OVF	R	0x0	If set, bytes counter reached overflow
1	PRBS_TX_CHK_CNT_MODE	R/W	0x0	PRBS Checker Mode 1b = Continuous mode 0b = Single Mode.
0	PRBS_TX_CHK_EN	R/W	0x0	If set, PRBS TX checker is enabled (PRBS TX checker is used in external reverse loop)

7.6.1.36 PRBS_TX_CHK_BYTE_CNT Register (Offset = 0x3A) [Reset = 0x0]

PRBS_TX_CHK_BYTE_CNT is shown in Table 7-47.

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Table 7-47 PRBS_TX_CHK_BYTE_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS_TX_CHK_BYTE_CNT	R	0x0	Holds number of total bytes that received by the PRBS TX checker. Value in this register is locked when write is done to register PRBS_TX_CHK_CTRL bit[7]or bit[8]. When PRBS Count Mode set to zero, count stops on 0xFFFF (see register 0x0016)

7.6.1.37 G_100BT_REG0 Register (Offset = 0x43) [Reset = 0x0]

G_100BT_REG0 is shown in Table 7-48.

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Table 7-48 G_100BT_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0x0	Reserved
11	RESERVED	R	0x0	Reserved
10-7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	RESERVED	R	0x0	Reserved
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2	RESERVED	R	0x0	Reserved
1	RESERVED	R	0x0	Reserved
0	FAST_RX_DV	R/W	0x0	Enable Fast RX_DV for low latency in 100Mbps mode. 0x0 = Fast rx dv disable 0x1 = Fast rx dv enable

7.6.1.38 G_1000BT_PMA_STATUS Register (Offset = 0x55) [Reset = 0x0]

G_1000BT_PMA_STATUS is shown in Table 7-49.

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Table 7-49 G_1000BT_PMA_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0x0	Reserved
7-4	PMA_MASTER_FIFO_CTRL	R	0x0	1000-Mb SFD Variation in Master Mode
3-0	PMA_SLAVE_FIFO_CTRL	R	0x0	1000-Mb SFD Variation in Slave Mode

7.6.1.39 STRAP_STS Register (Offset = 0x6E) [Reset = 0x0]

STRAP_STS is shown in Table 7-50.

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Table 7-50 STRAP_STS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0x0	Reserved
13	STRAP_LINK_LOSS_PASS_THRU	R	0x0	Link Loss Pass Through Enable Strap 0x0 = Enable 0x1 = Disable
12	STRAP_MIRROR_EN	R	0x0	Mirror Mode Enable Strap. 0x0 = Disable 0x1 = Enable
11-9	STRAP_OPMODE	R	0x0	OPMODE Strap 0x0 = RGMII To Copper
8-4	STRAP_PHY_ADD	R	0x0	PHY Address Strap
3-2	STRAP_ANEGSEL	R	0x0	Auto Negotiation Mode Select Strap. Refer to Strap Configuration Section
1	STRAP_ANEG_EN	R	0x0	Auto Negotiation Enable Strap 0x0 = Enable 0x1 = Disable
0	STRAP_RGMII_MII_SEL	R	0x0	RGMII to MII Enable Strap 0x0 = RGMII mode 0x1 = MII Mode

7.6.1.40 DBG_PRBS_BYTE_CNT Register (Offset = 0x71) [Reset = 0x0]

DBG_PRBS_BYTE_CNT is shown in Table 7-51.

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Table 7-51 DBG_PRBS_BYTE_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PRBS_BYTE_CNT	R	0x0	Holds number of total bytes that received by the PRBS checker. Value in this register is locked when write is done to register DBG_PRBS_ERR_CNT bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFF (see register 0x0016)

7.6.1.41 DBG_PRBS_ERR_CNT Register (Offset = 0x72) [Reset = 0x0]

DBG_PRBS_ERR_CNT is shown in Table 7-52.

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Table 7-52 DBG_PRBS_ERR_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0x0	Reserved
10	PRBS_PKT_CNT_OVF	R	0x0	If set, packet counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit #1of this register
9	PRBS_BYTE_CNT_OVF	R	0x0	If set, bytes counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit #1of this register
8	RESERVED	R	0x0	Reserved
7-0	PRBS_ERR_CNT	R	0x0	Holds number of errored bytes that received by the PRBS checker. Value in this register is locked when write is done to bit[0] or bit[1] (see bellow). When PRBS Count Mode set to zero, count stops on 0xFF (see register 0x0016) Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters

7.6.1.42 DBG_PKT_LEN_PRBS Register (Offset = 0x7B) [Reset = 0x5DC]

DBG_PKT_LEN_PRBS is shown in Table 7-53.

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Table 7-53 DBG_PKT_LEN_PRBS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PKT_LEN_PRBS	R/W	0x5DC	Length (in bytes) of PRBS packets, this effect the PRBS packets and not

7.6.1.43 ANA_RGMII_DLL_CTRL Register (Offset = 0x86) [Reset = 0x77]

ANA_RGMII_DLL_CTRL is shown in Table 7-54.

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Table 7-54 ANA_RGMII_DLL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0x0	Reserved
9	DLL_EN_FORCE_VAL	R/W	0x0	If dll_en_force_en is set, this is the value of DLL_EN
8	DLL_EN_FORCE_CTRL	R/W	0x0	Force DLL_EN value
7-4	DLL_TX_DELAY_CTRL_SL	R/W	0x7	Steps of 250ps, affects the CLK_90 output. - same behavior as bit [3:0]
3-0	DLL_RX_DELAY_CTRL_SL	R/W	0x7	Steps of 250ps, affects the CLK_90 output. b[3], b[2], b[1], b[0], shift, mode please note - the actual delay is also effected by the shift mode in reg 0x32 0x3 = 1.0ns, Shift 0x5 = 1.5ns, Shift 0x7 = 2.0 ns, Shift() - default 0x9 = 2.5ns, Shift 0xB = 3.0 ns,Shift 0xD = 3.5ns, Shift 0xF = 0ns, Align(*)

7.6.1.44 ANA_PLL_PROG_PI Register (Offset = 0xC6) [Reset = 0x0]

ANA_PLL_PROG_PI is shown in Table 7-55.

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Table 7-55 ANA_PLL_PROG_PI Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PLL_PROG_PI	R/W	0x0

7.6.1.45 LOOPCR Register (Offset = 0xFE) [Reset = 0xE721]

LOOPCR is shown in Table 7-56.

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Table 7-56 LOOPCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	FB_AEQ_CNT	R/W	0x7	AEQ max number of fallbacks
12-8	AEQ_MAX_STEP	R/W	0x7	The maximum step in aeq table
7-5	AEQ_STEP_SIZE	R/W	0x1	Increment step for aeq table
4-1	RESERVED	R	0x0
0	AEQ_BEG	R/W	0x1	Starting index for aeq table 0x0 = near-end loopback 0x1 = normal operation

7.6.1.46 RXF_CFG Register (Offset = 0x134) [Reset = 0x0]

RXF_CFG is shown in Table 7-57.

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Table 7-57 RXF_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0x0	Reserved
13	RESERVED	R	0x0	Reserved
12	RESERVED	R	0x0	Reserved
11	WOL_OUT_CLEAN	RH/WoP	0x0	If WOL out is in level mode in bit 8, writing to this bit will clear it.
10-9	WOL_OUT_STRETCH	R/W	0x0	If WOL out is in pulse mode in bit 8, this is the pulse length: 0x0 = 8 clock cycles 0x1 = 16 clock cycles 0x2 = 32 clock cycles 0x3 = 64 clock cycles
8	WOL_OUT_MODE	R/W	0x0	Mode of the wake up that goes to GPIO pin: 0x0 = Pulse Mode. 0x1 = Level Mode
7	ENHANCED_MAC_SUPPORT	R/W	0x0	Enables enhanced RX features. This bit should be set when using wakeup abilities, CRC check or RX 1588 indication
6	RESERVED	R	0x0	Reserved
5	RESERVED	R	0x0	Reserved
4	WAKE_ON_UCAST	R/W	0x0	If set, issue an interrupt upon reception of unicast packets
3	RESERVED	R	0x0	Reserved
2	WAKE_ON_BCAST	R/W	0x0	If set, issue an interrupt upon reception of broadcast packets
1	WAKE_ON_PATTERN	R/W	0x0	If set, issue an interrupt upon reception of a packet with configured pattern
0	WAKE_ON_MAGIC	R/W	0x0	If set, issue an interrupt upon reception of magic packet

7.6.1.47 RXF_STATUS Register (Offset = 0x135) [Reset = 0x0]

RXF_STATUS is shown in Table 7-58.

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Table 7-58 RXF_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0x0	Reserved
7	SFD_ERR	RC	0x0	SFD Error Detected
6	BAD_CRC	RC	0x0	Bad CRC Packet Received
5	RESERVED	R	0x0	Reserved
4	UCAST_RCVD	RC	0x0	Unicast Packet Received
3	RESERVED	R	0x0	Reserved
2	BCAST_RCVD	RC	0x0	Broadcast Packet Received
1	PATTERN_RCVD	RC	0x0	Pattern Match Packet Received
0	MAGIC_RCVD	RC	0x0	Magic Packet Received

7.6.1.48 IO_MUX_CFG Register (Offset = 0x170) [Reset = X]

IO_MUX_CFG is shown in Table 7-59.

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Table 7-59 IO_MUX_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0x0	Reserved
12-8	CLK_O_SEL	R/W	0xC	Select clock output source 0x0 = Channel A receive clock 0x1 = Channel B receive clock 0x2 = Channel C receive clock 0x3 = Channel D receive clock 0x4 = Channel A receive clock divided by 5 0x5 = Channel B receive clock divided by 5 0x6 = Channel C receive clock divided by 5 0x7 = Channel D receive clock divided by 5 0x8 = Channel A transmit clock 0x9 = Channel B transmit clock 0xA = Channel C transmit clock 0xB = Channel D transmit clock 0xC = Reference clock (synchronous to XI input clock)
7	RESERVED	R	0x0	Reserved
6	CLK_O_DISABLE	R/W	X	Clock Out Disable 0x0 = Clock Out Enable 0x1 = Clock Out Disable
5	RESERVED	R	0x0	Reserved
4-0	MAC_IMPEDANCE_CTRL	R/W	0x10	Impedance Control for MAC I/Os: Output impedance approximate range from 35-70 Ω in 32 steps. Lowest being 11111 and highest being 00000. Range and Step size will vary with process. Default is set to 50 Ω by trim but the default register value can vary by process. Non default values of MAC I/O impedance can be used based on trace impedance. Mismatch between device and trace impedance can cause voltage overshoot and undershoot. For RGMII mode, this should be set to 35 Ω (set to 11111)

7.6.1.49 TDR_GEN_CFG1 Register (Offset = 0x180) [Reset = 0x752]

TDR_GEN_CFG1 is shown in Table 7-60.

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Table 7-60 TDR_GEN_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0x0	Reserved
12	TDR_CH_CD_BYPASS	R/W	0x0	Bypass channel C and D in TDR tests
11	TDR_CROSS_MODE_DIS	R/W	0x0	If set, disable cross mode option - never check the cross (Listen only to the same channel you transmit)
10	TDR_NLP_CHECK	R/W	0x1	If set, check for NLPs during silence
9-7	TDR_AVG_NUM	R/W	0x6	Number Of TDR Cycles to Average: 000b = 1 TDR cycle 001b = 2 TDR cycles 010b = 4 TDR cycles 011b = 8 TDR cycles 100b = 16 TDR cycles 101b = 32 TDR cycles 110b = 64 TDR cycles (default) 111b = Reserved
6-4	TDR_SEG_NUM	R/W	0x5	Number of TDR segments to check
3-0	TDR_CYCLE_TIME	R/W	0x2	Number of micro-seconds in each TDR cycle

7.6.1.50 TDR_GEN_CFG2 Register (Offset = 0x181) [Reset = 0xC850]

TDR_GEN_CFG2 is shown in Table 7-61.

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Table 7-61 TDR_GEN_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_SILENCE_TH	R/W	0xC8	Energy detection threshold
7-6	TDR_POST_SILENCE_TIME	R/W	0x1	timer for tdr to look for energy after TDR transaction, if energy detected this is fail tdr
5-4	TDR_PRE_SILENCE_TIME	R/W	0x1	timer for tdr to look for energy before starting , if energy detected this is fail tdr
3-0	RESERVED	R	0x0	Reserved

7.6.1.51 TDR_SEG_DURATION1 Register (Offset = 0x182) [Reset = 0x5326]

TDR_SEG_DURATION1 is shown in Table 7-62.

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Table 7-62 TDR_SEG_DURATION1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0x0	Reserved
14-10	TDR_SEG_DURATION_SEG3	R/W	0x14	Number of 125MHz clock cycles to run for segment #3
9-5	TDR_SEG_DURATION_SEG2	R/W	0x19	Number of 125MHz clock cycles to run for segment #2
4-0	TDR_SEG_DURATION_SEG1	R/W	0x6	Number of 125MHz clock cycles to run for segment #1

7.6.1.52 TDR_SEG_DURATION2 Register (Offset = 0x183) [Reset = 0xA01E]

TDR_SEG_DURATION2 is shown in Table 7-63.

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Table 7-63 TDR_SEG_DURATION2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_SEG_DURATION_SEG5	R/W	0xA0	Number of 125MHz clock cycles to run for segment #5
7-6	RESERVED	R	0x0	Reserved
5-0	TDR_SEG_DURATION_SEG4	R/W	0x1E	Number of 125MHz clock cycles to run for segment #4

7.6.1.53 TDR_GEN_CFG3 Register (Offset = 0x184) [Reset = 0xE976]

TDR_GEN_CFG3 is shown in Table 7-64.

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Table 7-64 TDR_GEN_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	TDR_FWD_SHADOW_SEG4	R/W	0xE	Indicates how much time to wait after max level before declaring we found a peak in segment #4
11-8	TDR_FWD_SHADOW_SEG3	R/W	0x9	Indicates how much time to wait after max level before declaring we found a peak in segment #3
7	RESERVED	R	0x0	Reserved
6-4	TDR_FWD_SHADOW_SEG2	R/W	0x7	Indicates how much time to wait after max level before declaring we found a peak in segment #2
3	RESERVED	R	0x0	Reserved
2-0	TDR_FWD_SHADOW_SEG1	R/W	0x6	Indicates how much time to wait after max level before declaring we found a peak in segment #1

7.6.1.54 TDR_GEN_CFG4 Register (Offset = 0x185) [Reset = 0x19CF]

TDR_GEN_CFG4 is shown in Table 7-65.

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Table 7-65 TDR_GEN_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0x0	Reserved
13-11	TDR_SDW_AVG_LOC	R/W	0x3	how much to look between segments to search average peak
10-9	RESERVED	R	0x0	Reserved
8	TDR_TX_TYPE_SEG5	R/W	0x1	the tx type (10/100) for this segment
7	TDR_TX_TYPE_SEG4	R/W	0x1	the tx type (10/100) for this segment
6	TDR_TX_TYPE_SEG3	R/W	0x1	the tx type (10/100) for this segment
5	TDR_TX_TYPE_SEG2	R/W	0x0	the tx type (10/100) for this segment
4	TDR_TX_TYPE_SEG1	R/W	0x0	the tx type (10/100) for this segment
3-0	TDR_FWD_SHADOW_SEG5	R/W	0xF	Indicates how much time to wait after max level before declaring we found a peak in segment #5

7.6.1.55 TDR_PEAKS_LOC_A_0_1 Register (Offset = 0x190) [Reset = 0x0]

TDR_PEAKS_LOC_A_0_1 is shown in Table 7-66.

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Table 7-66 TDR_PEAKS_LOC_A_0_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_A_1	R	0x0	Found peak location 1 in channel A
7-0	TDR_PEAKS_LOC_A_0	R	0x0	Found peak location 0 in channel A

7.6.1.56 TDR_PEAKS_LOC_A_2_3 Register (Offset = 0x191) [Reset = 0x0]

TDR_PEAKS_LOC_A_2_3 is shown in Table 7-67.

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Table 7-67 TDR_PEAKS_LOC_A_2_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_A_3	R	0x0	Found peak location 3 in channel A
7-0	TDR_PEAKS_LOC_A_2	R	0x0	Found peak location 2 in channel A

7.6.1.57 TDR_PEAKS_LOC_A_4_B_0 Register (Offset = 0x192) [Reset = 0x0]

TDR_PEAKS_LOC_A_4_B_0 is shown in Table 7-68.

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Table 7-68 TDR_PEAKS_LOC_A_4_B_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_B_0	R	0x0	Found peak location 0 in channel B
7-0	TDR_PEAKS_LOC_A_4	R	0x0	Found peak location 4 in channel A

7.6.1.58 TDR_PEAKS_LOC_B_1_2 Register (Offset = 0x193) [Reset = 0x0]

TDR_PEAKS_LOC_B_1_2 is shown in Table 7-69.

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Table 7-69 TDR_PEAKS_LOC_B_1_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_B_2	R	0x0	Found peak location 2 in channel B
7-0	TDR_PEAKS_LOC_B_1	R	0x0	Found peak location 1 in channel B

7.6.1.59 TDR_PEAKS_LOC_B_3_4 Register (Offset = 0x194) [Reset = 0x0]

TDR_PEAKS_LOC_B_3_4 is shown in Table 7-70.

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Table 7-70 TDR_PEAKS_LOC_B_3_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_B_4	R	0x0	Found peak location 4 in channel B
7-0	TDR_PEAKS_LOC_B_3	R	0x0	Found peak location 3 in channel B

7.6.1.60 TDR_PEAKS_LOC_C_0_1 Register (Offset = 0x195) [Reset = 0x0]

TDR_PEAKS_LOC_C_0_1 is shown in Table 7-71.

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Table 7-71 TDR_PEAKS_LOC_C_0_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_C_1	R	0x0	Found peak location 1 in channel C
7-0	TDR_PEAKS_LOC_C_0	R	0x0	Found peak location 0 in channel C

7.6.1.61 TDR_PEAKS_LOC_C_2_3 Register (Offset = 0x196) [Reset = 0x0]

TDR_PEAKS_LOC_C_2_3 is shown in Table 7-72.

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Table 7-72 TDR_PEAKS_LOC_C_2_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_C_3	R	0x0	Found peak location 3 in channel C
7-0	TDR_PEAKS_LOC_C_2	R	0x0	Found peak location 2 in channel C

7.6.1.62 TDR_PEAKS_LOC_C_4_D_0 Register (Offset = 0x197) [Reset = 0x0]

TDR_PEAKS_LOC_C_4_D_0 is shown in Table 7-73.

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Table 7-73 TDR_PEAKS_LOC_C_4_D_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_D_0	R	0x0	Found peak location 0 in channel D
7-0	TDR_PEAKS_LOC_C_4	R	0x0	Found peak location 4 in channel C

7.6.1.63 TDR_PEAKS_LOC_D_1_2 Register (Offset = 0x198) [Reset = 0x0]

TDR_PEAKS_LOC_D_1_2 is shown in Table 7-74.

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Table 7-74 TDR_PEAKS_LOC_D_1_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_D_2	R	0x0	Found peak location 2 in channel D
7-0	TDR_PEAKS_LOC_D_1	R	0x0	Found peak location 1 in channel D

7.6.1.64 TDR_PEAKS_LOC_D_3_4 Register (Offset = 0x199) [Reset = 0x0]

TDR_PEAKS_LOC_D_3_4 is shown in Table 7-75.

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Table 7-75 TDR_PEAKS_LOC_D_3_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	TDR_PEAKS_LOC_D_4	R	0x0	Found peak location 4 in channel D
7-0	TDR_PEAKS_LOC_D_3	R	0x0	Found peak location 3 in channel D

7.6.1.65 TDR_GEN_STATUS Register (Offset = 0x1A4) [Reset = 0x0]

TDR_GEN_STATUS is shown in Table 7-76.

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Table 7-76 TDR_GEN_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0x0	Reserved
11	TDR_P_LOC_CROSS_MODE_D	R	0x0	Peak found at cross mode in channel D
10	TDR_P_LOC_CROSS_MODE_C	R	0x0	Peak found at cross mode in channel C
9	TDR_P_LOC_CROSS_MODE_B	R	0x0	Peak found at cross mode in channel B
8	TDR_P_LOC_CROSS_MODE_A	R	0x0	Peak found at cross mode in channel A
7	TDR_P_LOC_OVERFLOW_D	R	0x0	Total number of peaks in current segment reached max value of 5 in channel D
6	TDR_P_LOC_OVERFLOW_C	R	0x0	Total number of peaks in current segment reached max value of 5 in channel C
5	TDR_P_LOC_OVERFLOW_B	R	0x0	Total number of peaks in current segment reached max value of 5 in channel B
4	TDR_P_LOC_OVERFLOW_A	R	0x0	Total number of peaks in current segment reached max value of 5 in channel A
3	TDR_SEG1_HIGH_CROSS_D	R	0x0	Peak crossed high threshold of segment #1 in channel D
2	TDR_SEG1_HIGH_CROSS_C	R	0x0	peak crossed high threshold of segment #1 in channel C
1	TDR_SEG1_HIGH_CROSS_B	R	0x0	peak crossed high threshold of segment #1 in channel B
0	TDR_SEG1_HIGH_CROSS_A	R	0x0	peak crossed high threshold of segment #1 in channel A

7.6.1.66 TDR_PEAKS_SIGN_A_B Register (Offset = 0x1A5) [Reset = 0x0]

TDR_PEAKS_SIGN_A_B is shown in Table 7-77.

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Table 7-77 TDR_PEAKS_SIGN_A_B Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0x0	Reserved
9	TDR_PEAKS_SIGN_B_4	R	0x0	found peaks sign 4 in channel B
8	TDR_PEAKS_SIGN_B_3	R	0x0	found peaks sign 3 in channel B
7	TDR_PEAKS_SIGN_B_2	R	0x0	found peaks sign 2 in channel B
6	TDR_PEAKS_SIGN_B_1	R	0x0	found peaks sign 1 in channel B
5	TDR_PEAKS_SIGN_B_0	R	0x0	found peaks sign 0 in channel B
4	TDR_PEAKS_SIGN_A_4	R	0x0	found peaks sign 4 in channel A
3	TDR_PEAKS_SIGN_A_3	R	0x0	found peaks sign 3 in channel A
2	TDR_PEAKS_SIGN_A_2	R	0x0	found peaks sign 2 in channel A
1	TDR_PEAKS_SIGN_A_1	R	0x0	found peaks sign 1 in channel A
0	TDR_PEAKS_SIGN_A_0	R	0x0	found peaks sign 0 in channel A

7.6.1.67 TDR_PEAKS_SIGN_C_D Register (Offset = 0x1A6) [Reset = 0x0]

TDR_PEAKS_SIGN_C_D is shown in Table 7-78.

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Table 7-78 TDR_PEAKS_SIGN_C_D Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0x0	Reserved
9	TDR_PEAKS_SIGN_D_4	R	0x0	found peaks sign 4 in channel D
8	TDR_PEAKS_SIGN_D_3	R	0x0	found peaks sign 3 in channel D
7	TDR_PEAKS_SIGN_D_2	R	0x0	found peaks sign 2 in channel D
6	TDR_PEAKS_SIGN_D_1	R	0x0	found peaks sign 1 in channel D
5	TDR_PEAKS_SIGN_D_0	R	0x0	found peaks sign 0 in channel D
4	TDR_PEAKS_SIGN_C_4	R	0x0	found peaks sign 4 in channel C
3	TDR_PEAKS_SIGN_C_3	R	0x0	found peaks sign 3 in channel C
2	TDR_PEAKS_SIGN_C_2	R	0x0	found peaks sign 2 in channel C
1	TDR_PEAKS_SIGN_C_1	R	0x0	found peaks sign 1 in channel C
0	TDR_PEAKS_SIGN_C_0	R	0x0	found peaks sign 0 in channel C

7.6.1.68 MASK_SOFT_RST Register (Offset = 0x1D6) [Reset = 0xFFFF]

MASK_SOFT_RST is shown in Table 7-79.

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Table 7-79 MASK_SOFT_RST Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MASK_SOFTRST	R/W	0xFFFF	Mask for inputs which can trigger internal soft reset recovery mechanism

7.6.1.69 MASK_EXTERNAL_INT Register (Offset = 0x1D7) [Reset = 0xFFFF]

MASK_EXTERNAL_INT is shown in Table 7-80.

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Table 7-80 MASK_EXTERNAL_INT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MASK_EXT_INT	R/W	0xFFFF	Mask for inputs which can trigger external recovery mechanism(INT_STTMCHNE_N)

7.6.1.70 SEU_STATUS_REG Register (Offset = 0x1D8) [Reset = 0x0]

SEU_STATUS_REG is shown in Table 7-81.

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Table 7-81 SEU_STATUS_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	USE_LATER	R	0x0	Currently connected to 0. Will be used later.
11	PLL_LOCK_DET_FAIL	R	0x0
10	SYS_CLK_FREQ_LOCK_LOST	R	0x0	status bit latched high when frequency lock is lost on sys_clk. Cleared when you write 1 to this bit or on POR or on pin reset
9	SYS_CLK_PPM_LOCK_LOST	R	0x0	status bit latched high when ppm lock is lost on sys_clk. Cleared when you write 1 to this bit or on POR or on pin reset
8	SYS_CLK_INACTIVE	R	0x0	status bit latched high when sys_clk is inactive. Cleared when you write 1 to this bit or on POR or on pin reset
7	LD_TX_CLK_INACTIVE	R	0x0	status bit latched high when ld_tx_clk is inactive. Cleared when you write 1 to this bit or on POR or on pin reset
6	PLL_CLK_FREQ_LOCK_LOST	R	0x0	status bit latched high when frequency lock is lost on pll clock (125Mhz). Cleared when you write 1 to this bit or on POR or on pin reset
5	PLL_CLK_PPM_LOCK_LOST	R	0x0	status bit latched high when ppm lock is lost for pll clock (125Mhz). Cleared when you write 1 to this bit or on POR or on pin reset
4	PLL_CLK_INACTIVE	R	0x0	status bit latched high when pll clock (125Mhz) is inactive. Cleared when you write 1 to this bit or on POR or on pin reset
3	PLL_250_RECV_CLK_INACTIVE	R	0x0	status bit latched high when 250M pll recovered clock is inactive. Cleared when you write 1 to this bit or on POR or on pin reset
2	ADC_CLK_INACTIVE	R	0x0	status bit latched high when adc clock on any channel is inactive. Cleared when you write 1 to this bit or on POR or on pin reset
1	FAULT_DET_PM_TOP	R	0x0	status bit latched high when a fault is detected in ep_pm_top block. Cleared when you write 1 to this bit or on POR or on pin reset
0	FAULT_DET_RESET_CTRL	R	0x0	status bit latched high when a fault is detected in ep_reset_ctrl block. Cleared when you write 1 to this bit or on POR or on pin reset

7.6.1.71 REF_CLK_PPM_MONITOR_CNT Register (Offset = 0x1D9) [Reset = 0x30D3]

REF_CLK_PPM_MONITOR_CNT is shown in Table 7-82.

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Table 7-82 REF_CLK_PPM_MONITOR_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0x0	Reserved
13-0	CFG_REF_CLK_PPM_MONITOR_COUNT	R/W	0x30D3	Number of cycles for which counter running on reference(25Mhz) clock should run to calculate ppm (By default counter takes 0.5ms)

7.6.1.72 MON_CLK_PPM_MONITOR_CNT Register (Offset = 0x1DA) [Reset = 0xF423]

MON_CLK_PPM_MONITOR_CNT is shown in Table 7-83.

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Table 7-83 MON_CLK_PPM_MONITOR_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	CFG_MON_CLK_PPM_MONITOR_COUNT	R/W	0xF423	Number of cycles for which counter running on clock which has to be monitored(125Mhz) should run by the time reference counter does a rollback (By default counter takes 0.5ms if there is zero ppm)

7.6.1.73 MAX_PLUS_PPM_MON_CNT Register (Offset = 0x1DB) [Reset = 0x44]

MAX_PLUS_PPM_MON_CNT is shown in Table 7-84.

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Table 7-84 MAX_PLUS_PPM_MON_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	CFG_PLUS_PPM_MAX_MON_CNT	R/W	0x44	when the reference counter goes to zero value, the maximum value of mon_cnt(as it is + ppm, mon_cnt rolls back) for a threshold of 1000ppm

7.6.1.74 MAX_MINUS_PPM_MON_CNT Register (Offset = 0x1DC) [Reset = 0xF3DF]

MAX_MINUS_PPM_MON_CNT is shown in Table 7-85.

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Table 7-85 MAX_MINUS_PPM_MON_CNT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	CFG_MINUS_PPM_MAX_MON_CNT	R/W	0xF3DF	when the reference counter goes to zero value, the minimum value of mon_cnt(as it is - ppm, mon_cnt doesn't roll back) for a threshold of 1000ppm

7.6.1.75 SYS_CLK_PPM_STATUS Register (Offset = 0x1DD) [Reset = 0xF423]

SYS_CLK_PPM_STATUS is shown in Table 7-86.

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Table 7-86 SYS_CLK_PPM_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	SYS_CLK_PPM_STATUS	R	0xF423	every time reference counter rolls back, the value of monitor count is latched into this status register. Use this register to get an approximate value of ppm. Don't use this register to calculate ppm if seu_stat[10]==1

7.6.1.76 PLL_CLK_PPM_STATUS Register (Offset = 0x1DE) [Reset = 0xF423]

PLL_CLK_PPM_STATUS is shown in Table 7-87.

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Table 7-87 PLL_CLK_PPM_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	PLL_CLK_PPM_STATUS	R	0xF423	every time reference counter rolls back, the value of monitor count is latched into this status register. Use this register to get an approximate value of ppm. Don't use this register to calculate ppm if seu_stat[6]==1

7.6.1.77 OP_MODE_DECODE Register (Offset = 0x1DF) [Reset = 0x0]

OP_MODE_DECODE is shown in Table 7-88.

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Table 7-88 OP_MODE_DECODE Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0x0	Reserved
8-7	RESERVED	R	0x0	Reserved
6	RESERVED	R	0x0	Reserved
5	RGMII_MII_SEL	R/W	0x0	0x0 = RGMII 0x1 = MII
4	RESERVED	R	0x0	Reserved
3	RESERVED	R	0x0	Reserved
2-0	CFG_OPMODE	R/W	0x0	Operation Mode 0x0 = RGMII to Copper 0x1 = Reserved 0x2 = Reserved 0x3 = Reserved 0x4 = Reserved 0x5 = Reserved 0x6 = Reserved 0x7 = Reserved

7.6.1.78 GPIO_MUX_CTRL Register (Offset = 0x1E0) [Reset = 0x7A]

GPIO_MUX_CTRL is shown in Table 7-89.

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Table 7-89 GPIO_MUX_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0x0	Reserved
11-8	RESERVED	R	0x0	Reserved
7-4	JTAG_TDO_GPIO_1_CTRL	R/W	0x7	See bits [3:0] for GPIO control options. If either type of SFD is enabled, this pin will be automatically configured to TX_SFD.
3-0	LED_2_GPIO_0_CTRL	R/W	0xA	Following options are available for GPIO control. If either type of SFD is enabled, this pin will be automatically configured to RX_SFD. 0x0 = CLK_OUT 0x1 = RESERVED 0x2 = INT 0x3 = Link status 0x4 = RESERVED 0x5 = Transmit SFD 0x6 = Receive SFD 0x7 = WOL 0x8 = Energy detect(1000Base-T and 100Base-TX only) 0x9 = PRBS errors 0xA = LED_2 0xB = LED_GPIO(3) 0xC = CRS 0xD = COL 0xE = constant '0' 0xF = constant '1'

7.6.1.79 MONITOR_REGISTERS_0 Register (Offset = 0x1E2) [Reset = 0x25]

MONITOR_REGISTERS_0 is shown in Table 7-90.

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Table 7-90 MONITOR_REGISTERS_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CFG_SNSR_DC_OFFSET_SEL	R/W	0x0	Controls the DC offset value for monitors 0x0 = DC offset is from calibration logic 0x1 = DC offset is taken from 0x1E7[15-8]
14	CFG_SNSR_SEFIINT_EN	R/W	0x0	Reserved
13-11	CFG_SNSR_SEFIDET_THRESH	R/W	0x0	Reserved
10-9	CFG_SNSR_HISTDET_THRESH	R/W	0x0	Reserved
8-7	CFG_SNSR_SCALE_ADC_INP	R/W	0x0	Reserved
6	CFG_SNSR_HIST_CLR	R/W	0x0	Writing 1 to this bit clears the history of monitor data samples collected to detect SEFI event. This is not a self-clear bit. Write 0 to clear this bit
5	CFG_SNSR_DISCARD_SAMPLE_NUM	R/W	0x1	Controls number of sensor ADC symbols to discard after enabling the ADC and before starting the averaging for further logging 0x0 = 3 samples 0x1 = 6 samples
4	CFG_SNSR_AVG_SAMPLE_NUM	R/W	0x0	Controls number of sensor ADC symbols to average for further logging 0x0 = 3 samples 0x1 = 5 samples
3-2	CFG_SNSR_ADC_CLK_DIV	R/W	0x1	Controls the frequency of sensor ADC input clock 0x0 = 12.5MHz 0x1 = 6.25MHz 0x2 = 3.125MHz 0x3 = 3.125MHz
1	CFG_SNSR_FORCE_START	R/W	0x0	Set this bit to forcefully enable the sensor monitors. Normally the monitors are enabled after Link up on MDI
0	CFG_SNSR_RESET	R/W	0x1	Set this bit to manually put the monitors in a reset state

7.6.1.80 MONITOR_REGISTERS_1 Register (Offset = 0x1E7) [Reset = 0x12]

MONITOR_REGISTERS_1 is shown in Table 7-91.

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Table 7-91 MONITOR_REGISTERS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	CFG_SNSR_DC_OFFSET_2C	R/W	0x0	Controls the Sensor DC offset if 0x1E2[15] is set to 1.
7-6	CFG_SNSR_CIC_GAIN12_ARITH	R/W	0x0
5-3	CFG_SNSR_CIC_GAIN2	R/W	0x2
2-0	CFG_SNSR_CIC_GAIN1	R/W	0x2

7.6.1.81 MONITOR_REGISTERS_2 Register (Offset = 0x1E8) [Reset = 0x920]

MONITOR_REGISTERS_2 is shown in Table 7-92.

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Table 7-92 MONITOR_REGISTERS_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CFG_SNSR_BYPASS_RESET_SENSOR_VAL	R/W	0x0	Controls the reset value to sensor if monitor FSM is bypassed by setting register bit 0x1E9[14] 0x0 = sensor is in reset state 0x1 = Sensor is not in reset
14-12	CFG_SNSR_RD_DATA	R/W	0x0	Controls the sensor from which data is read from register 0x1EA 0x0 = data is read from VDDA2P5 sensor 0x1 = data is read from VDDA1P8 sensor 0x2 = data is read from VDD1P1 sensor 0x3 = data is read from VDDIO sensor 0x4 = data is read from Temperature sensor 0x5 = reserved 0x6 = reserved 0x7 = reserved
11-9	CFG_SNSR_DEC_FACTOR_SENSORS	R/W	0x4	Controls the decimation factor for sensor ADC when the monitor is working in normal mode and out of calibration phase
8-6	CFG_SNSR_DEC_FACTOR_GAIN_CALIB	R/W	0x4	Controls the decimation factor for sensor ADC when the monitor is in gain calibration stage
5-3	CFG_SNSR_DEC_FACTOR_DC_CALIB	R/W	0x4	Controls the decimation factor for sensor ADC when the monitor is in DC calibration stage
2-0	CFG_SNSR_BYPASS_SEL_NUM	R/W	0x0	This field selects the sensor to be monitored when FSM is bypassed by setting register bit 0x1E9[14]

7.6.1.82 MONITOR_REGISTERS_3 Register (Offset = 0x1E9) [Reset = 0x36D]

MONITOR_REGISTERS_3 is shown in Table 7-93.

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Table 7-93 MONITOR_REGISTERS_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CFG_SNSR_GAIN_NOTFROM_EFUSE	R/W	0x0	If set, selects the gain for sensors from configuration registers and not from efuse. Refer to registers 0x1E7[7:0] 0x0 = Gain values are taken from EFUSE 0x1 = Gain values are not taken from EFUSE
14	CFG_SNSR_BYPASS_FSM	R/W	0x0	Control bit to bypass the monitor FSM logic 0x0 = Monitor FSM is controlling the sensors 0x1 = Monitor FSM is bypassed
13-12	CFG_SNSR_ITER_TIMES	R/W	0x0	This field determines the number of times the sensors programmed in 0x1E9[11:0] should be cycled through before checking all sensors
11-9	CFG_SNSR_ITER_SLOT_3	R/W	0x1	selects the sensor for slot 3 in each iteration before all sensors are checked
8-6	CFG_SNSR_ITER_SLOT_2	R/W	0x5	selects the sensor for slot 2 in each iteration before all sensors are checked
5-3	CFG_SNSR_ITER_SLOT_1	R/W	0x5	selects the sensor for slot 1 in each iteration before all sensors are checked
2-0	CFG_SNSR_ITER_SLOT_0	R/W	0x5	selects the sensor for slot 0 in each iteration before all sensors are checked

7.6.1.83 MONITOR_REGISTERS_RD_0 Register (Offset = 0x1EA) [Reset = 0x0]

MONITOR_REGISTERS_RD_0 is shown in Table 7-94.

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Table 7-94 MONITOR_REGISTERS_RD_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	STAT_SNSR_RD_RDATA	R	0x0	Read back data from sensors can be logged from this register. Data from particular sensor can be read by bypassing the FSM using register bit 0x1E9[14] and selecting particular sensor by programming 0x1E8[2:0]

7.6.1.84 LOCK_DET_REG Register (Offset = 0x1EE) [Reset = 0x35]

LOCK_DET_REG is shown in Table 7-95.

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Table 7-95 LOCK_DET_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	NEWBITFIELD	R/W	0x0
9	CFG_CRC_EN	R/W	0x0
8	CFG_ECC_EN	R/W	0x0	Harsh Industrial only: In harsh industrial mode, enable the ECC and Checksum protection of programmable register bank.
7	CFG_ECC_ERR_EN	R/W	0x0	Harsh Industrial only: In harsh industrial mode, enable the ECC and Checksum protection of programmable register bank. When cfg_ecc_en is set, setting this bit, will create error.
6-4	CFG_PROG_LOCKDET_WINDOW	R/W	0x3
3-2	CFG_PROG_LOCKDET_WAIT	R/W	0x1
1	CFG_FORCE_PLL_LOCK_DET_MON_EN	R/W	0x0
0	CFG_PLL_LOCK_DET_MON_EN	R/W	0x1

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7.6.1 DP83561SP Registers

7.6.1.1 BMCR Register (Offset = 0x0) [Reset = 0x1140]

7.6.1.2 BMSR Register (Offset = 0x1) [Reset = 0x7949]

7.6.1.3 PHYIDR1 Register (Offset = 0x2) [Reset = 0x2000]

7.6.1.4 PHYIDR2 Register (Offset = 0x3) [Reset = 0xA1A4]

7.6.1.5 ANAR Register (Offset = 0x4) [Reset = 0x1E1]

7.6.1.6 ALNPAR Register (Offset = 0x5) [Reset = 0x0]

7.6.1.7 ANER Register (Offset = 0x6) [Reset = 0x64]

7.6.1.8 ANNPTR Register (Offset = 0x7) [Reset = 0x2001]

7.6.1.9 ANLNPTR Register (Offset = 0x8) [Reset = 0x2001]

7.6.1.10 GEN_CFG1 Register (Offset = 0x9) [Reset = 0x300]

7.6.1.11 GEN_STATUS1 Register (Offset = 0xA) [Reset = 0x0]

7.6.1.12 REGCR Register (Offset = 0xD) [Reset = 0x0]

7.6.1.13 ADDAR Register (Offset = 0xE) [Reset = 0x0]

7.6.1.14 1KSCR Register (Offset = 0xF) [Reset = 0xF000]

7.6.1.15 PHY_CONTROL Register (Offset = 0x10) [Reset = 0x5048]

7.6.1.16 PHY_STATUS Register (Offset = 0x11) [Reset = 0x0]

7.6.1.17 INTERRUPT_MASK Register (Offset = 0x12) [Reset = 0x0]

7.6.1.18 INTERRUPT_STATUS Register (Offset = 0x13) [Reset = 0x0]

7.6.1.19 GEN_CFG2 Register (Offset = 0x14) [Reset = 0x2947]

7.6.1.20 RX_ERR_CNT Register (Offset = 0x15) [Reset = 0x0]

7.6.1.21 BIST_CONTROL Register (Offset = 0x16) [Reset = 0x0]

7.6.1.22 GEN_STATUS2 Register (Offset = 0x17) [Reset = 0x40]

7.6.1.23 LEDS_CFG1 Register (Offset = 0x18) [Reset = 0x6150]

7.6.1.24 LEDS_CFG2 Register (Offset = 0x19) [Reset = 0x4444]

7.6.1.25 LEDS_CFG3 Register (Offset = 0x1A) [Reset = 0x2]

7.6.1.26 GEN_CFG4 Register (Offset = 0x1E) [Reset = 0x2]

7.6.1.27 GEN_CTRL Register (Offset = 0x1F) [Reset = 0x0]

7.6.1.28 ANALOG_TEST_CTRL Register (Offset = 0x25) [Reset = 0x480]

7.6.1.29 GEN_CFG_ENH_AMIX Register (Offset = 0x2C) [Reset = 0x141F]

7.6.1.30 GEN_CFG_FLD Register (Offset = 0x2D) [Reset = 0x0]

7.6.1.31 GEN_CFG_FLD_THR Register (Offset = 0x2E) [Reset = 0x221]

7.6.1.32 GEN_CFG3 Register (Offset = 0x31) [Reset = 0x0]

7.6.1.33 RGMII_CTRL Register (Offset = 0x32) [Reset = 0xD0]

7.6.1.34 RGMII_CTRL2 Register (Offset = 0x33) [Reset = 0x0]

7.6.1.35 PRBS_TX_CHK_CTRL Register (Offset = 0x39) [Reset = 0x0]

7.6.1.36 PRBS_TX_CHK_BYTE_CNT Register (Offset = 0x3A) [Reset = 0x0]

7.6.1.37 G_100BT_REG0 Register (Offset = 0x43) [Reset = 0x0]

7.6.1.38 G_1000BT_PMA_STATUS Register (Offset = 0x55) [Reset = 0x0]

7.6.1.39 STRAP_STS Register (Offset = 0x6E) [Reset = 0x0]

7.6.1.40 DBG_PRBS_BYTE_CNT Register (Offset = 0x71) [Reset = 0x0]

7.6.1.41 DBG_PRBS_ERR_CNT Register (Offset = 0x72) [Reset = 0x0]

7.6.1.42 DBG_PKT_LEN_PRBS Register (Offset = 0x7B) [Reset = 0x5DC]

7.6.1.43 ANA_RGMII_DLL_CTRL Register (Offset = 0x86) [Reset = 0x77]

7.6.1.44 ANA_PLL_PROG_PI Register (Offset = 0xC6) [Reset = 0x0]

7.6.1.45 LOOPCR Register (Offset = 0xFE) [Reset = 0xE721]

7.6.1.46 RXF_CFG Register (Offset = 0x134) [Reset = 0x0]

7.6.1.47 RXF_STATUS Register (Offset = 0x135) [Reset = 0x0]

7.6.1.48 IO_MUX_CFG Register (Offset = 0x170) [Reset = X]

7.6.1.49 TDR_GEN_CFG1 Register (Offset = 0x180) [Reset = 0x752]

7.6.1.50 TDR_GEN_CFG2 Register (Offset = 0x181) [Reset = 0xC850]

7.6.1.51 TDR_SEG_DURATION1 Register (Offset = 0x182) [Reset = 0x5326]

7.6.1.52 TDR_SEG_DURATION2 Register (Offset = 0x183) [Reset = 0xA01E]

7.6.1.53 TDR_GEN_CFG3 Register (Offset = 0x184) [Reset = 0xE976]

7.6.1.54 TDR_GEN_CFG4 Register (Offset = 0x185) [Reset = 0x19CF]

7.6.1.55 TDR_PEAKS_LOC_A_0_1 Register (Offset = 0x190) [Reset = 0x0]

7.6.1.56 TDR_PEAKS_LOC_A_2_3 Register (Offset = 0x191) [Reset = 0x0]

7.6.1.57 TDR_PEAKS_LOC_A_4_B_0 Register (Offset = 0x192) [Reset = 0x0]

7.6.1.58 TDR_PEAKS_LOC_B_1_2 Register (Offset = 0x193) [Reset = 0x0]

7.6.1.59 TDR_PEAKS_LOC_B_3_4 Register (Offset = 0x194) [Reset = 0x0]

7.6.1.60 TDR_PEAKS_LOC_C_0_1 Register (Offset = 0x195) [Reset = 0x0]

7.6.1.61 TDR_PEAKS_LOC_C_2_3 Register (Offset = 0x196) [Reset = 0x0]

7.6.1.62 TDR_PEAKS_LOC_C_4_D_0 Register (Offset = 0x197) [Reset = 0x0]

7.6.1.63 TDR_PEAKS_LOC_D_1_2 Register (Offset = 0x198) [Reset = 0x0]

7.6.1.64 TDR_PEAKS_LOC_D_3_4 Register (Offset = 0x199) [Reset = 0x0]

7.6.1.65 TDR_GEN_STATUS Register (Offset = 0x1A4) [Reset = 0x0]

7.6.1.66 TDR_PEAKS_SIGN_A_B Register (Offset = 0x1A5) [Reset = 0x0]

7.6.1.67 TDR_PEAKS_SIGN_C_D Register (Offset = 0x1A6) [Reset = 0x0]

7.6.1.68 MASK_SOFT_RST Register (Offset = 0x1D6) [Reset = 0xFFFF]

7.6.1.69 MASK_EXTERNAL_INT Register (Offset = 0x1D7) [Reset = 0xFFFF]

7.6.1.70 SEU_STATUS_REG Register (Offset = 0x1D8) [Reset = 0x0]

7.6.1.71 REF_CLK_PPM_MONITOR_CNT Register (Offset = 0x1D9) [Reset = 0x30D3]

7.6.1.72 MON_CLK_PPM_MONITOR_CNT Register (Offset = 0x1DA) [Reset = 0xF423]

7.6.1.73 MAX_PLUS_PPM_MON_CNT Register (Offset = 0x1DB) [Reset = 0x44]

7.6.1.74 MAX_MINUS_PPM_MON_CNT Register (Offset = 0x1DC) [Reset = 0xF3DF]

7.6.1.75 SYS_CLK_PPM_STATUS Register (Offset = 0x1DD) [Reset = 0xF423]