ZHCSNO0B April   2021  – November 2021 DP83561-SP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin States
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
      1. 6.6.1 Timing Requirement Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Engineering Model (Parts With /EM Suffix)
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Copper Ethernet
        1. 7.3.1.1 1000BASE-T
        2. 7.3.1.2 100BASE-TX
        3. 7.3.1.3 10BASE-Te
      2. 7.3.2 MAC Interfaces
        1. 7.3.2.1 Reduced GMII (RGMII)
          1. 7.3.2.1.1 RGMII-TX Requirements
          2. 7.3.2.1.2 RGMII-RX Requirements
          3. 7.3.2.1.3 1000-Mbps Mode Operation
          4. 7.3.2.1.4 1000-Mbps Mode Timing
          5. 7.3.2.1.5 10- and 100-Mbps Mode
        2. 7.3.2.2 Media Independent Interface (MII)
      3. 7.3.3 Auto-Negotiation
        1. 7.3.3.1 Speed and Duplex Selection - Priority Resolution
        2. 7.3.3.2 Master and Slave Resolution
        3. 7.3.3.3 Pause and Asymmetrical Pause Resolution
        4. 7.3.3.4 Next Page Support
        5. 7.3.3.5 Parallel Detection
        6. 7.3.3.6 Restart Auto-Negotiation
        7. 7.3.3.7 Enabling Auto-Negotiation Through Software
        8. 7.3.3.8 Auto-Negotiation Complete Time
        9. 7.3.3.9 Auto-MDIX Resolution
      4. 7.3.4 Speed Optimization
      5. 7.3.5 Radiation Performance
        1. 7.3.5.1 Total Ionizing Dose (TID)
        2. 7.3.5.2 Single-Event Effects (SEE)
        3. 7.3.5.3 Single Event Functional Interrupt (SEFI) Monitor Suite
          1. 7.3.5.3.1 PCS State Machine Monitors
          2. 7.3.5.3.2 Configuration Register Monitors
          3. 7.3.5.3.3 Temperature Monitor
          4. 7.3.5.3.4 PLL Lock Monitor
      6. 7.3.6 WoL (Wake-on-LAN) Packet Detection
        1. 7.3.6.1 Magic Packet Structure
        2. 7.3.6.2 Magic Packet Example
        3. 7.3.6.3 Wake-on-LAN Configuration and Status
      7. 7.3.7 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 7.3.7.1 SFD Latency Variation and Determinism
          1. 7.3.7.1.1 1000M SFD Variation in Master Mode
          2. 7.3.7.1.2 1000M SFD Variation in Slave Mode
          3. 7.3.7.1.3 100M SFD Variation
      8. 7.3.8 Cable Diagnostics
        1. 7.3.8.1 TDR
        2. 7.3.8.2 Fast Link Drop
        3. 7.3.8.3 Fast Link Detect
        4. 7.3.8.4 Energy Detect
        5. 7.3.8.5 IEEE 802.3 Test Modes
        6. 7.3.8.6 Jumbo Frames
      9. 7.3.9 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Mirror Mode
      2. 7.4.2 Loopback Mode
        1. 7.4.2.1 Near-End Loopback
          1. 7.4.2.1.1 MII Loopback
          2. 7.4.2.1.2 PCS Loopback
          3. 7.4.2.1.3 Digital Loopback
          4. 7.4.2.1.4 Analog Loopback
          5. 7.4.2.1.5 External Loopback
          6. 7.4.2.1.6 Far-End (Reverse) Loopback
        2. 7.4.2.2 Loopback Availability Exception
      3. 7.4.3 Power-Saving Modes
        1. 7.4.3.1 IEEE Power Down
        2. 7.4.3.2 Deep Power-Down Mode
        3. 7.4.3.3 Active Sleep
        4. 7.4.3.4 Passive Sleep
    5. 7.5 Programming
      1. 7.5.1 Serial Management Interface
        1. 7.5.1.1 Extended Address Space Access
          1. 7.5.1.1.1 Write Address Operation
          2. 7.5.1.1.2 Read Address Operation
          3. 7.5.1.1.3 Write (No Post Increment) Operation
          4. 7.5.1.1.4 Read (No Post Increment) Operation
          5. 7.5.1.1.5 Write (Post Increment) Operation
          6. 7.5.1.1.6 Read (Post Increment) Operation
          7. 7.5.1.1.7 Example of Read Operation Using Indirect Register Access
          8. 7.5.1.1.8 Example of Write Operation Using Indirect Register Access
      2. 7.5.2 Interrupt
      3. 7.5.3 BIST Configuration
      4. 7.5.4 Strap Configuration
      5. 7.5.5 LED Configuration
      6. 7.5.6 LED Operation From 1.8-V I/O VDD Supply
      7. 7.5.7 Reset Operation
        1. 7.5.7.1 Hardware Reset
        2. 7.5.7.2 IEEE Software Reset
        3. 7.5.7.3 Global Software Reset
        4. 7.5.7.4 Global Software Restart
        5. 7.5.7.5 PCS Restart
    6. 7.6 Register Maps
      1. 7.6.1 DP83561SP Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clock Input
          1. 8.2.2.1.1 Crystal Recommendations
          2. 8.2.2.1.2 External Clock Source Recommendations
        2. 8.2.2.2 MAC Interface
          1. 8.2.2.2.1 RGMII Layout Guidelines
          2. 8.2.2.2.2 MII Layout Guidelines
        3. 8.2.2.3 Media Dependent Interface (MDI)
          1. 8.2.2.3.1 MDI Layout Guidelines
        4. 8.2.2.4 Magnetics Requirements
          1. 8.2.2.4.1 Magnetics Connection
  9. 9 Power Supply Recommendations
    1. 9.1 Two-Supply Configuration
    2. 9.2 Three-Supply Configuration
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Traces
      2. 10.1.2 Return Path
      3. 10.1.3 Transformer Layout
      4. 10.1.4 Metal Pour
      5. 10.1.5 PCB Layer Stacking
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

For Assembly, please refer to package drawing section

Figure 5-1 HBE Package 64-Pin CQFP Top View
Table 5-1 Pin Functions
PIN I/O TYPE(1) DESCRIPTION
NO. NAME

1

Reserved

I/O

Reserved. Keep it NC

2

TD_P_A

I/O

A

Differential Transmit and Receive Signals

3

TD_M_A

I/O

A

Differential Transmit and Receive Signals

4

VDDA2P5_1

I

A

2.5-V Analog Supply (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

5

TD_P_B

I/O

A

Differential Transmit and Receive Signals

6

TD_M_B

I/O

A

Differential Transmit and Receive Signals

7

Reserved

I

A

Reserved. Keep it NC

8

VDD1P1_1

I

A

1.1-V Digital Supply (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

9

Reserved

I

A

Reserved. Keep it NC

10

TD_P_C

I/O

A

Differential Transmit and Receive Signals

11

TD_M_C

I/O

A

Differential Transmit and Receive Signals

12

VDDA2P5_2

I

A

2.5-V Analog Supply (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

13

TD_P_D

I/O

A

Differential Transmit and Receive Signals

14

TD_M_D

I/O

A

Differential Transmit and Receive Signals

15

RBIAS

I

A

Bias Resistor Connection. A 10-kΩ ±1% resistor should be connected from RBIAS to GND. A 90-pF ±10% capacitor should be connected in parallel with the bias resistor.

16

VDDA1P8_1

I

A

In three-supply mode, an external 1.8-V (±5%) supply can be connected to these pins. When using an external supply, each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

In two supply mode, no external supply is required for this pin.

When unused, no connections should be made to these pins.

17

Reserved

-

A

Reserved. Keep it NC

18

Reserved

-

A

Reserved. Keep it NC

19

Reserved

-

A

Reserved. Keep it NC

20

Reserved

-

A

Reserved. Keep it NC

21

VDDIO_SEL_1

I

A, S

VDDIO_SEL1/ VDDIO_SEL0:

00 (Default): VDDIO 3V3

01: Reserve

10: VDDIO 2V5

11: VDDIO 1V8

22

VDDIO_SEL_0

I

A, S

23

SUPPLYMODE_SEL

S

0 = Dual supply mode (VDDA1P8 left floating) (Default)

1 = Triple supply mode (VDDA1P8 supplied by system)

24

VDDIO_1

I

A

I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

25

XO

O

A

CRYSTAL OSCILLATOR OUTPUT: Second terminal for 25-MHz crystal. Must be left floating if a clock oscillator is used.

26

XI

I

A

CRYSTAL OSCILLATOR INPUT: 25-MHz oscillator or crystal input.

27

Reserved

-

A

Reserved. Keep it NC

28

JTAG_CLK

I

PU

JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity.

29

JTAG_TDO/GPIO_1

O

PD

JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device through TDO. General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.

This pin should be pulled down by a 2.49-kΩ resistor.

30

JTAG_TMS

I

PU

JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends that the user apply 3 clock cycles with JTAG_TMS high to reset the JTAG.

31

JTAG_TDI

I

PU

JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device through the TDI.

32

COL/GPIO_2

I/O

PD

COLLISION DETECT: Asserted high to indicate detection of a collision condition (assertion of CRS due to simultaneous transmit and receive activity) in Half-Duplex modes. This signal is not synchronous to either MII clock (GTX_CLK, TX_CLK or RX_CLK). (Default) General Purpose I/O: This signal provides a multi-function configurable I/O. Refer to the GPIO_MUX_CTRL register for details.

33

CRS/GPIO_3

I/O

PD, S

CARRIER SENSE: CRS is asserted high to indicate the presence of a carrier due to receive or transmit activity in Half-Duplex mode. (Default) General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.

34

AUTO_RECOVER

I

PD, S

0 = DP83561-SP will take no automatic action based on SEFI. SEFI event interrupts will be generated normally. (Default)

1 = Configures the DP83561-SP to automatically apply RESET signal to PHY logic when a SEFI is detected by one of the monitors configured (STATE_MACHINE, temperature monitor, PLL lock, ECC registers). Default register values will be reloaded and pin options. SEFI event interrupts will be generated normally.

35

TX_D3

I

PD

TRANSMIT DATA: Signal TX_D [3:0] carries data from the MAC to the PHY in RGMII mode and MII mode. Data is synchronous to the transmit clock.

36

TX_D2

I

PD

37

TX_D1

I

PD

38

TX_D0

I

PD

39

GTX_CLK/TX_CLK

I/O

PD/O

RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125 MHz in 1000-Mbps mode. This pin will be Input in RGMII mode.

MII TRANSMIT CLOCK: In MII mode, this pin provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. This pin will be output in MII mode.

This pin will be GTX_CLK by default and can be changed to TX_CLK by register configurations. Selection of the MII MAC interface also changes the GTX_CLK/TX_CLK selection without any additional register writes needed.

40

VDDIO_2

I

A

I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

41

VDD1P1_2

I

A

1.1-V Digital Supply (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

42

RX_CLK

O

PD

RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation:

125 MHz in 1000-Mbps RGMII mode.

25 MHz in 100-Mbps RGMII/MII mode.

2.5 MHz in 10-Mbps RGMII/MII mode.

When PHY is not linked, this pin provides 2.5-MHz clock for both RGMII/MII mode.

43

RX_ER

O

PD

MII Mode: In MII mode this pin will be configured as RX_ER. This pin is asserted high synchronously to rising edge of RX_CLK. Use of this pin is optional.

44

RX_D0

O

PD, S

RECEIVE DATA: Signal RX_D [3:0] carries data from the PHY to the MAC in RGMII mode and in MII mode. Symbols received on the cable are decoded and presented on these pins synchronous to RX_CLK.

RX_D2 and RX_D3 should be pulled down by a 2.49-kΩ resistor.

45

RX_D1

O

PD, S

46

RX_D2

O

PD

47

RX_D3

O

PD

48

TX_EN/TX_CTRL

I

PD

TX_EN: In MII mode, this pin will function as TX_EN.

TRANSMIT CONTROL: In RGMII mode, TX_CTRL combines the transmit enable and the transmit error signal inputs from the MAC using both clock edges.

49

RX_DV/RX_CTRL

O

PD, S

RX_DV: In MII mode, this pin will function as RX_DV.

RECEIVE CONTROL: In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK).

50

SMI_DISABLE

I

PD, S

0 = SMI (MDIO) writes are enabled. (Default)

1 = Station Management Interface (MDIO) writes are disabled.

51

VDD1P1_3

I

A

1.1-V Digital Supply (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

52

CLK_OUT

O

O

CLOCK OUTPUT: Output clock

53

MDIO

I/O

-

MANAGEMENT DATA I/O: Bidirectional management instruction/data signal that may be sourced by the management station or the PHY. This open-drain pin requires a 2.2- kΩ pullup resistor.

54

MDC

I

-

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 24 MHz. There is no minimum clock rate.

55

INT_STTMCHNE_N

O

OD

STATE MACHINE INTERRUPT: This pin will be asserted low when an invalid state machine transition, condition, or other invalid condition is detected. When operating this pin as an open-drain interrupt, an external 2.2-kΩ resistor connected to the VDDIO supply is recommended.

56

INT_ECC_N

O

OD

ECC INTERRUPT: This pin will be asserted low when a configuration register error is detected or corrected by register ECC. When operating this pin as an open-drain interrupt, an external 2.2-kΩ resistor connected to the VDDIO supply is recommended.

57

INT_SUP_CUR_N

O

OD

SUPPLY CURRENT INTERRUPT: This pin will be asserted low when an abnormal supply current is detected during normal operation. When operating this pin as an open-drain interrupt, an external 2.2-kΩ resistor connected to the VDDIO supply is recommended.

58

VDDIO_3

I

A

I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

59

RESET_N

I

PU, S

RESET_N: This pin is an active-low reset input that initializes or re-initializes all the internal registers of the DP83561-SP. Asserting this pin low for at least 1 µs will force a reset process to occur.

60

PWDN_N/INT_N

I/O

PU

PWDN_N (Default): This is an Active Low Input. Asserting this signal low enables the power-down mode of operation. In this mode, the device powers down and consumes minimum power. Register access is available through the Management Interface to configure and power up the device.

INT_N: The interrupt pin is an open-drain, active low output signal indicating an interrupt condition has occurred. Register access is required to determine which event caused the interrupt. TI recommends using an external 2.2-kΩ resistor connected to the VDDIO supply. When register access is disabled through pin option, the interrupt will be asserted for 500 ms before self-clearing.

61

LED_2/GPIO_0

O

S

LED_2: This pin is part of the VDDIO voltage domain. Default functionality is RX/TX activity

General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.

62

LED_1

O

S

LED_1: This pin is part of the VDDIO voltage domain. Default functionality is 1000BT link is up.

63

LED_0

O

S

LED_0: This pin is part of the VDDIO voltage domain. Default functionality is Link OK.

64

VDDA1P8_2

I

A

No external supply is required for this pin in two-supply mode. When unused, no connections should be made to these pins. In three-supply mode, an external 1.8-V (±5%) supply can be connected to these pins. When using an external supply, each pin requires a 1-µF and 0.1-µF capacitor to GND. Refer to Section 9 for more details.

DAP

DAP

-

GND

DIE ATTACH PAD, connect to GND(2)
(1) The functionality of the pins are defined below:
  • Type I: Input
  • Type O: Output
  • Type I/O: Input /Output
  • Type PD or PU: Internal Pull-down or Pull-up
  • Type S: Strap Configuration Pin
  • Type A: Analog pins
(2) The metal lid is internally grounded and attached to the DAP