ZHCSRW1A
february 2023 – august 2023
AM69
,
AM69A
ADVANCE INFORMATION
1
1
特性
2
应用
3
说明
3.1
功能方框图
4
Revision History
5
Device Comparison
6
Terminal Configuration and Functions
6.1
Pin Diagrams
6.2
Pin Attributes
11
12
6.3
Signal Descriptions
14
6.3.1
ADC
6.3.1.1
MCU Domain
17
18
19
6.3.2
DDRSS
6.3.2.1
MAIN Domain
22
23
24
25
6.3.3
GPIO
6.3.3.1
MAIN Domain
28
6.3.3.2
WKUP Domain
30
6.3.4
I2C
6.3.4.1
MAIN Domain
33
34
35
36
37
38
39
6.3.4.2
MCU Domain
41
42
6.3.4.3
WKUP Domain
44
6.3.5
I3C
6.3.5.1
MCU Domain
47
6.3.6
MCAN
6.3.6.1
MAIN Domain
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
6.3.6.2
MCU Domain
69
70
6.3.7
MCSPI
6.3.7.1
MAIN Domain
73
74
75
76
77
78
79
6.3.7.2
MCU Domain
81
82
6.3.8
UART
6.3.8.1
MAIN Domain
85
86
87
88
89
90
91
92
93
94
6.3.8.2
MCU Domain
96
6.3.8.3
WKUP Domain
98
6.3.9
MDIO
6.3.9.1
MAIN Domain
101
102
6.3.9.2
MCU Domain
104
6.3.10
UFS
6.3.10.1
MAIN Domain
107
6.3.11
CPSW2G
6.3.11.1
MAIN Domain
110
6.3.11.2
MCU Domain
112
6.3.12
SGMII
6.3.12.1
MAIN Domain
115
6.3.13
ECAP
6.3.13.1
MAIN Domain
118
119
120
6.3.14
EQEP
6.3.14.1
MAIN Domain
123
124
125
6.3.15
EPWM
6.3.15.1
MAIN Domain
128
129
130
131
132
133
134
6.3.16
USB
6.3.16.1
MAIN Domain
137
6.3.17
Display Port
6.3.17.1
MAIN Domain
140
6.3.18
Hyperlink
6.3.18.1
MAIN Domain
143
144
145
6.3.19
PCIE
6.3.19.1
MAIN Domain
148
6.3.20
SERDES
6.3.20.1
MAIN Domain
151
152
153
154
6.3.21
DSI
6.3.21.1
MAIN Domain
157
158
6.3.22
CSI
6.3.22.1
MAIN Domain
161
162
163
6.3.23
MCASP
6.3.23.1
MAIN Domain
166
167
168
169
170
6.3.24
DMTIMER
6.3.24.1
MAIN Domain
173
6.3.24.2
MCU Domain
175
6.3.25
CPTS
6.3.25.1
MAIN Domain
178
6.3.25.2
MCU Domain
180
6.3.26
DSS
6.3.26.1
MAIN Domain
183
6.3.27
GPMC
6.3.27.1
MAIN Domain
186
6.3.28
MMC
6.3.28.1
MAIN Domain
189
190
6.3.29
OSPI
6.3.29.1
MCU Domain
193
194
6.3.30
Hyperbus
6.3.30.1
MCU Domain
197
6.3.31
Emulation and Debug
6.3.31.1
MAIN Domain
200
201
6.3.32
System and Miscellaneous
6.3.32.1
Boot Mode configuration
204
6.3.32.2
Clock
206
207
6.3.32.3
System
209
210
6.3.32.4
EFUSE
212
6.3.32.5
VMON
214
6.3.33
Power
216
6.4
Pin Connectivity Requirements
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Power-On-Hour (POH) Limits
7.4
Recommended Operating Conditions
7.5
运行性能点
7.6
Electrical Characteristics
7.6.1
I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
7.6.2
Fail-Safe Reset (FS Reset) Electrical Characteristics
7.6.3
HFOSC/LFOSC Electrical Characteristics
7.6.4
eMMCPHY Electrical Characteristics
7.6.5
SDIO Electrical Characteristics
7.6.6
CSI2/DSI D-PHY Electrical Characteristics
7.6.7
ADC12B Electrical Characteristics
7.6.8
LVCMOS Electrical Characteristics
7.6.9
USB2PHY Electrical Characteristics
7.6.10
SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
7.6.11
UFS M-PHY Electrical Characteristics
7.6.12
eDP/DP AUX-PHY Electrical Characteristics
7.6.13
DDR0 Electrical Characteristics
7.7
VPP Specifications for One-Time Programmable (OTP) eFuses
7.7.1
Recommended Operating Conditions for OTP eFuse Programming
7.7.2
Hardware Requirements
7.7.3
Programming Sequence
7.7.4
Impact to Your Hardware Warranty
7.8
Thermal Resistance Characteristics
7.8.1
Thermal Resistance Characteristics for ALY Package
7.9
Temperature Sensor Characteristics
7.10
Timing and Switching Characteristics
7.10.1
Timing Parameters and Information
7.10.2
Power Supply Sequencing
7.10.2.1
Power Supply Slew Rate Requirement
7.10.2.2
Combined MCU and Main Domains Power- Up Sequencing
7.10.2.3
Combined MCU and Main Domains Power- Down Sequencing
7.10.2.4
Isolated MCU and Main Domains Power- Up Sequencing
7.10.2.5
Isolated MCU and Main Domains Power- Down Sequencing
7.10.2.6
Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
7.10.2.7
Independent MCU and Main Domains, Entry and Exit of DDR Retention State
7.10.2.8
Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
7.10.3
System Timing
7.10.3.1
Reset Timing
7.10.3.2
Safety Signal Timing
7.10.3.3
Clock Timing
7.10.4
Clock Specifications
7.10.4.1
Input and Output Clocks / Oscillators
7.10.4.1.1
WKUP_OSC0 Internal Oscillator Clock Source
7.10.4.1.1.1
Load Capacitance
7.10.4.1.1.2
Shunt Capacitance
7.10.4.1.2
WKUP_OSC0 LVCMOS Digital Clock Source
7.10.4.1.3
Auxiliary OSC1 Internal Oscillator Clock Source
7.10.4.1.3.1
Load Capacitance
7.10.4.1.3.2
Shunt Capacitance
7.10.4.1.4
Auxiliary OSC1 LVCMOS Digital Clock Source
7.10.4.1.5
Auxiliary OSC1 Not Used
7.10.4.2
Output Clocks
7.10.4.3
PLLs
7.10.4.4
Module and Peripheral Clocks Frequencies
7.10.5
Peripherals
7.10.5.1
ATL
7.10.5.1.1
ATL_PCLK Timing Requirements
7.10.5.1.2
ATL_AWS[x] Timing Requirements
7.10.5.1.3
ATL_BWS[x] Timing Requirements
7.10.5.1.4
ATCLK[x] Switching Characteristics
7.10.5.2
CPSW2G
7.10.5.2.1
CPSW2G MDIO Interface Timings
7.10.5.2.2
CPSW2G RMII Timings
7.10.5.2.2.1
CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
7.10.5.2.2.2
CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
7.10.5.2.2.3
CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
7.10.5.2.3
CPSW2G RGMII Timings
7.10.5.2.3.1
RGMII[x]_RXC Timing Requirements – RGMII Mode
7.10.5.2.3.2
CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
7.10.5.2.3.3
CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
7.10.5.2.3.4
RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
7.10.5.3
CSI-2
7.10.5.4
DDRSS
7.10.5.5
DSS
7.10.5.6
eCAP
7.10.5.6.1
Timing Requirements for eCAP
7.10.5.6.2
Switching Characteristics for eCAP
7.10.5.7
EPWM
7.10.5.7.1
Timing Requirements for eHRPWM
7.10.5.7.2
Switching Characteristics for eHRPWM
7.10.5.8
eQEP
7.10.5.8.1
Timing Requirements for eQEP
7.10.5.8.2
Switching Characteristics for eQEP
7.10.5.9
GPIO
7.10.5.9.1
GPIO Timing Requirements
7.10.5.9.2
GPIO Switching Characteristics
7.10.5.10
GPMC
7.10.5.10.1
GPMC and NOR Flash — Synchronous Mode
7.10.5.10.1.1
GPMC and NOR Flash Timing Requirements — Synchronous Mode
7.10.5.10.1.2
GPMC and NOR Flash Switching Characteristics – Synchronous Mode
7.10.5.10.2
GPMC and NOR Flash — Asynchronous Mode
7.10.5.10.2.1
GPMC and NOR Flash Timing Requirements – Asynchronous Mode
7.10.5.10.2.2
GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
7.10.5.10.3
GPMC and NAND Flash — Asynchronous Mode
7.10.5.10.3.1
GPMC and NAND Flash Timing Requirements – Asynchronous Mode
7.10.5.10.3.2
GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
7.10.5.10.4
GPMC0 IOSET
7.10.5.11
HyperBus
7.10.5.11.1
Timing Requirements for HyperBus
7.10.5.11.2
HyperBus 166 MHz Switching Characteristics
7.10.5.11.3
HyperBus 100 MHz Switching Characteristics
7.10.5.12
I2C
7.10.5.13
I3C
7.10.5.14
MCAN
7.10.5.15
MCASP
7.10.5.16
MCSPI
7.10.5.16.1
MCSPI — Controller Mode
7.10.5.16.2
MCSPI — Peripheral Mode
7.10.5.17
MMCSD
7.10.5.17.1
MMC0 - eMMC Interface
7.10.5.17.1.1
Legacy SDR Mode
7.10.5.17.1.2
High Speed SDR Mode
7.10.5.17.1.3
High Speed DDR Mode
7.10.5.17.1.4
HS200 Mode
7.10.5.17.1.5
HS400 Mode
7.10.5.17.2
MMC1/2 - SD/SDIO Interface
7.10.5.17.2.1
Default Speed Mode
7.10.5.17.2.2
High Speed Mode
7.10.5.17.2.3
UHS–I SDR12 Mode
7.10.5.17.2.4
UHS–I SDR25 Mode
7.10.5.17.2.5
UHS–I SDR50 Mode
7.10.5.17.2.6
UHS–I DDR50 Mode
7.10.5.17.2.7
UHS–I SDR104 Mode
7.10.5.18
CPTS
7.10.5.18.1
CPTS Timing Requirements
7.10.5.18.2
CPTS Switching Characteristics
7.10.5.19
OSPI
7.10.5.19.1
OSPI0 PHY Mode
7.10.5.19.1.1
OSPI With Data Training
7.10.5.19.1.1.1
OSPI Switching Characteristics – Data Training
7.10.5.19.1.2
OSPI Without Data Training
7.10.5.19.1.2.1
OSPI Timing Requirements – SDR Mode
7.10.5.19.1.2.2
OSPI Switching Characteristics – SDR Mode
7.10.5.19.1.2.3
OSPI Timing Requirements – DDR Mode
7.10.5.19.1.2.4
OSPI Switching Characteristics – DDR Mode
7.10.5.19.2
OSPI0 Tap Mode
7.10.5.19.2.1
OSPI0 Tap SDR Timing
7.10.5.19.2.2
OSPI0 Tap DDR Timing
7.10.5.20
OLDI
7.10.5.20.1
OLDI Switching Characteristics
7.10.5.21
PCIE
7.10.5.22
Timers
7.10.5.22.1
Timing Requirements for Timers
7.10.5.22.2
Switching Characteristics for Timers
7.10.5.23
UART
7.10.5.23.1
Timing Requirements for UART
7.10.5.23.2
UART Switching Characteristics
7.10.5.24
USB
7.10.6
Emulation and Debug
7.10.6.1
Trace
7.10.6.2
JTAG
7.10.6.2.1
JTAG Electrical Data and Timing
7.10.6.2.1.1
JTAG Timing Requirements
7.10.6.2.1.2
JTAG Switching Characteristics
8
Detailed Description
8.1
Overview
8.2
功能方框图
8.3
Processor Subsystems
8.3.1
Arm Cortex-A72
8.3.2
Arm Cortex-R5F
8.3.3
DSP C71x
8.4
Accelerators and Coprocessors
8.4.1
GPU
8.4.2
VPAC
8.4.3
DMPAC
8.5
Other Subsystems
8.5.1
MSMC
8.5.2
NAVSS
8.5.2.1
NAVSS0
8.5.2.2
MCU_NAVSS
8.5.3
PDMA Controller
8.5.4
Power Supply
8.5.5
Peripherals
8.5.5.1
ADC
8.5.5.2
ATL
8.5.5.3
CSI
8.5.5.3.1
Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
8.5.5.3.2
Camera Streaming Interface Transmitter (CSI_TX_IF)
8.5.5.4
CPSW2G
8.5.5.5
CPSW9G
8.5.5.6
DCC
8.5.5.7
DDRSS
8.5.5.8
DSS
8.5.5.8.1
DSI
8.5.5.8.2
eDP
8.5.5.9
VPFE
8.5.5.10
eCAP
8.5.5.11
EPWM
8.5.5.12
ELM
8.5.5.13
ESM
8.5.5.14
eQEP
8.5.5.15
GPIO
8.5.5.16
GPMC
8.5.5.17
Hyperbus
8.5.5.18
I2C
8.5.5.19
I3C
8.5.5.20
MCAN
8.5.5.21
MCASP
8.5.5.22
MCRC Controller
8.5.5.23
MCSPI
8.5.5.24
MMC/SD
8.5.5.25
OSPI
8.5.5.26
PCIE
8.5.5.27
SerDes
8.5.5.28
WWDT
8.5.5.29
Timers
8.5.5.30
UART
8.5.5.31
USB
8.5.5.32
UFS
9
Applications, Implementation, and Layout
10
Device Connection and Layout Fundamentals
10.1
Power Supply Decoupling and Bulk Capacitors
10.1.1
Power Distribution Network Implementation Guidance
10.2
External Oscillator
10.3
JTAG and EMU
10.4
Reset
10.5
Unused Pins
10.6
Hardware Design Guide for JacintoTM 7 Devices
11
Peripheral- and Interface-Specific Design Information
11.1
LPDDR4 Board Design and Layout Guidelines
11.2
OSPI and QSPI Board Design and Layout Guidelines
11.2.1
No Loopback and Internal Pad Loopback
11.2.2
External Board Loopback
11.2.3
DQS (only available in Octal Flash devices)
11.3
USB VBUS Design Guidelines
11.4
System Power Supply Monitor Design Guidelines using VMON/POK
11.5
High Speed Differential Signal Routing Guidance
11.6
Thermal Solution Guidance
12
Device and Documentation Support
12.1
Device Nomenclature
12.1.1
Standard Package Symbolization
12.1.2
Device Naming Convention
12.2
Tools and Software
12.3
支持资源
12.4
Trademarks
12.5
静电放电警告
12.6
术语表
13
Mechanical, Packaging, and Orderable Information
13.1
Packaging Information
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
ALY|1414
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsrw1a_oa
Table 6-30 MCAN8 Signal Descriptions
SIGNAL NAME [
1
]
PIN TYPE [
2
]
DESCRIPTION [
3
]
ALY PIN [
4
]
MCAN8_RX
I
MCAN Receive Data
AD37
,
AF34
MCAN8_TX
O
MCAN Transmit Data
AC37
,
AJ36