ZHCSMQ8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. 7 Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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6.9 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
D0+, D0–, D1+, D1–, D2+, D2–, CLK+, and CLK–
tR/FInput rise and fall timeRXEN at VDD; see Figure 7-4800ps
ΔtR/FInput rise or fall time mismatch between all SubLVDS inputstR(n) – tR(m) and tF(n) – tF(m) with
n = {D0, D1, D2, or CLK} and
m = {D0, D1, D2, or CLK}		–100100ps
R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE
tR/FRise and fall time
20% to 80% of VDD(2)		CL = 10 pF(3)
(see Figure 7-3)		1-channel mode, F/S = L816ns
2-channel mode, F/S = L48
3-channel mode, F/S = L48
1-channel mode, F/S = H48
2-channel mode, F/S = H12
3-channel mode, F/S = H12
tOUTPPCLK output duty cycle1-channel and 3-channel mode45%50%55%
CPOL = VIL, 2-channel mode48%53%59%
CPOL = VIH, 2-channel mode41%47%52%
tOSKOutput skew from PCLK to R[0:7], G[0:7], B0:7], HS, VS, and DEsee Figure 7-3–500500ps
INPUT TO OUTPUT RESPONSE TIME
tPD(L)Propagation delay time from CLK+ input to PCLK outputRXEN at VDD, VIH = VDD, VIL = GND, CL = 10 pF, see Figure 7-81.4 / fPCLK1.9 / fPCLK2.5 / fPCLKs
tGSRXEN glitch suppression pulse width(4)VIH = VDD, VIL = GND, RXEN toggles from
VIL to VIH; see Figure 7-9 and Figure 7-10		3.8μs
tpwrupEnable time from power down (↑RXEN)Time from RXEN pulled high to data outputs enabled and outputs valid data; see Figure 7-102ms
tpwrdnDisable time from active mode (↓RXEN)RXEN is pulled low during receive mode;
time measurement until all outputs held static:
R[0:7] = G[0:7] = B[0:7] = VS = HS = high,
DE = PCLK = low and PLL is Shutdown; see Figure 7-10		11μs
twakeupEnable time from Standby (↑↓CLK)RXEN at VDD; device is in standby; time measurement from CLK input starts switching to PCLK and data outputs enabled and outputting valid data; see Figure 7-112ms
tsleepDisable time from active mode (CLK transitions to high-impedance)RXEN at VDD; device is receiving data; time measurement from CLK input signal stops (input open or input common mode VICM exceeds threshold voltage Vthstby) until all outputs held static: R[0:7] = G[0:7] = B[0:7] = VS = HS = high,
DE = PCLK = low and PLL is Shutdown;
see Figure 7-11		3μs
fBWPLL bandwidth(5)Tested from CLK input to PCLK output2-ChM; fPCLK = 22 MHz0.087 × fPCLKMHz
3-ChM; fPCLK = 65 MHz0.075 × fPCLK
(1) All typical values are at 25°C and with 1.8-V supply unless otherwise noted.
(2) tR/F depends on the F/S setting and the capacitive load connected to each output. Some application information of how to calculate tR/F based on the output load and how to estimate the timing budget to interconnect to an LCD driver are provided in the application section near the end of this data sheet.
(3) The output rise and fall time is optimized for an output load of 10 pF. The rise and fall time can be adjusted by changing the output load capacitance.
(4) The RXEN input incorporates a glitch-suppression logic to disregard short input pulses. tGS is the duration of either a high-to-low or low-to-high transition that is suppressed.
(5) When using the SN65LVDS302 receiver in conjunction with the SN65LVDS301 transmitter in one link, the PLL bandwidth of the SN65LVDS302 receiver always exceed the bandwidth of the SN65LVDS301 transmit PLL. This ensures stable PLL tracking under all operating conditions and maximizes the receiver skew margin.