ZHCSMQ8E
june 2006 – october 2020
SN65LVDS302
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Input Electrical Characteristics
6.7
Output Electrical Characteristics
6.8
Timing Requirements
6.9
Switching Characteristics
6.10
Device Power Dissipation
Typical Characteristics
7
Parameter Measurement Information
20
7.1
Power Consumption Tests
7.2
Typical IC Power Consumption Test Pattern
7.3
Maximum Power Consumption Test Pattern
7.4
Output Skew Pulse Position and Jitter Performance
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Swap Pin Functionality
8.3.2
Parity Error Detection and Handling
8.4
Device Functional Modes
8.4.1
Deserialization Modes
8.4.1.1
1-Channel Mode
8.4.1.2
2-Channel Mode
8.4.1.3
3-Channel Mode
8.4.2
Powerdown Modes
8.4.2.1
Shutdown Mode
8.4.2.2
Standby Mode
8.4.3
Active Modes
8.4.3.1
Acquire Mode (PLL Approaches Lock)
8.4.3.2
Receive Mode
8.4.4
Status Detect and Operating Modes Flow
9
Application and Implementation
9.1
Application Information
9.1.1
Application Information
9.1.2
Preventing Increased Leakage Currents in Control Inputs
9.1.3
Calculation Example: HVGA Display
9.1.4
How to Determine Interconnect Skew and Jitter Budget
9.1.5
F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
9.1.6
How to Determine the LCD Driver Timing Margin
9.1.7
Typical Application Frequencies
9.2
Typical Applications
9.2.1
VGA Application
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Power-Up and Power-Down Sequences
9.2.1.3
Application Curves
9.2.2
Dual LCD-Display Application
9.2.2.1
Design Requirements
9.2.2.2
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
12
Device and Documentation Support
12.1
Community Resource
12.2
Trademarks
13
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
ZXH|80
MPBGAI9
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsmq8e_oa
zhcsmq8e_pm
1
特性
串行接口技术
与
FlatLink™
3G 兼容,例如 SN65LVDS301
支持在 1、2 或 3 条 SubLVDS 差分线路上接收高达 24 位 RGB 数据和 3 个控制位的视频接口
SubLVDS 差分电压电平
数据吞吐量高达 1.755Gbps
三种节能工作模式
有源模式 QVGA:17mW
典型关断:0.7μW
典型待机模式:27μW(典型值)
通过总线交换功能提高 PCB 布局灵活性
ESD 等级 > 4kV (HBM)
像素时钟范围为 4MHz 至 65MHz
所有 CMOS 输入的失效防护
采用 5mm × 5mm nFBGA 封装,0.5mm 焊球间距
极低的电磁干扰 (EMI),符合 SAE J1752/3 'Kh' 技术规范