ZHCSMQ8E june   2006  – october 2020 SN65LVDS302

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Output Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Device Power Dissipation
    11.     Typical Characteristics
  8. Parameter Measurement Information
    1.     20
    2. 7.1 Power Consumption Tests
    3. 7.2 Typical IC Power Consumption Test Pattern
    4. 7.3 Maximum Power Consumption Test Pattern
    5. 7.4 Output Skew Pulse Position and Jitter Performance
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Error Detection and Handling
    4. 8.4 Device Functional Modes
      1. 8.4.1 Deserialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
        1. 8.4.2.1 Shutdown Mode
        2. 8.4.2.2 Standby Mode
      3. 8.4.3 Active Modes
        1. 8.4.3.1 Acquire Mode (PLL Approaches Lock)
        2. 8.4.3.2 Receive Mode
      4. 8.4.4 Status Detect and Operating Modes Flow
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Information
      2. 9.1.2 Preventing Increased Leakage Currents in Control Inputs
      3. 9.1.3 Calculation Example: HVGA Display
      4. 9.1.4 How to Determine Interconnect Skew and Jitter Budget
      5. 9.1.5 F/S Pin Setting and Connecting the SN65LVDS302 to an LCD Driver
      6. 9.1.6 How to Determine the LCD Driver Timing Margin
      7. 9.1.7 Typical Application Frequencies
    2. 9.2 Typical Applications
      1. 9.2.1 VGA Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power-Up and Power-Down Sequences
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Dual LCD-Display Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 Community Resource
    2. 12.2 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

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说明

SN65LVDS302 接收器将与 FlatLink™3G 兼容的串行输入数据解串为 27 个并行数据输出。SN65LVDS302 接收器包含一个移位寄存器,在检查奇偶校验位之后,此寄存器从 1、2 或 3 个串行输入载入 30 位,并且将 24 个像素位和 3 个控制位锁存至并行 CMOS 输出。如果奇偶校验确认奇偶校验正确,通道奇偶校验错误 (CPE) 输出保持低电平。如果检测到奇偶校验错误,CPE 输出生成一个高脉冲,而数据输出总线忽略刚刚接收到的像素。或者,最后一个数据字在下一个时钟周期内被保持在输出总线上。

器件信息(1)
器件型号封装封装尺寸(标称值)
SN65LVDS302nFBGA (80)5.00mm × 5.00mm
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GUID-6EF70F85-7D5C-4BA4-B841-1F03E3C5A844-low.gif实现示例